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ADM7150

Data Sheet

VIN (V)

+125°C

+25°C

–40°C

1.0

1.2

1.4

1.6

1.8

2.0

2.2

2.4

Figure 59. Typical EN Fall Threshold vs. Input Voltage (VIN) for Various

Temperatures

The ADM7150 also incorporates an internal undervoltage

lockout circuit to disable the output voltage when the input

voltage is less than the minimum input voltage rating of the

regulator. The upper and lower thresholds are internally fixed

with about 300 mV of hysteresis.

VIN (V)

4.5

4.4

4.0

4.2

4.3

4.1

3.5

3.0

2.5

2.0

1.5

1.0

0.5

VOUT_VIN_RISE

VOUT_VIN_FALL

Figure 60. Typical UVLO Hysteresis, VOUT = 3.3 V

Figure 60 shows the typical hysteresis of the UVLO function.

This hysteresis prevents on/off oscillations that can occur due to

noise on the input voltage as it passes through the threshold

points.

START-UP TIME

The ADM7150 uses an internal soft start to limit the inrush

current when the output is enabled. The start-up time for a 5 V

output is approximately 3 ms from the time the EN active threshold

is crossed to when the output reaches 90% of its final value.

The rise time of the output voltage (10% to 90%) is approximately

0.0012 × CBYP seconds

where CBYP is in microfarads.

TIME (Seconds)

0.020

0.016

0.008

0.012

0.004

0.018

0.014

0.006

0.010

0.002

ENABLE

CBYP = 1µF

CBYP = 4.7µF

CBYP = 10µF

Figure 61. Typical Start-Up Behavior with CBYP = 1 µF to 10 µF

TIME (Seconds)

0.20

0.16

0.08

0.12

0.04

0.18

0.14

0.06

0.10

0.02

ENABLE

CBYP = 10µF

CBYP = 47µF

CBYP = 330µF

Figure 62. Typical Start-Up Behavior with CBYP = 10 µF to 330 µF

REF, BYP, AND, VREG PINS

REF, BYP, and VREG are internally generated voltages that

require external bypass capacitors for proper operation. Do not,

under any circumstances, connect any loads to these pins because

doing so compromises the noise and PSRR performance of the

ADM7150. Using larger values of CBYP, CREF, and CREG is acceptable

but can increase the start-up time as described in the Start-Up

Time section.

Rev. 0 | Page 18 of 24

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