Matrix LED Display Driver

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17

The multiplexing scheme drives digits 0 and 1 at the

same time, then digits 2 and 3 at the same time. To

increase the effective brightness of the displays, drive

only two digits instead of four. By doing this, the aver-

age segment current doubles, but also doubles the

number of MAX6953s required to drive a given number

of digits.

Because digit 1 is driven at the same time as digit 0

(and digit 3 is driven at the same time as digit 2), only 1

bit is used to set the scan limit. The bit is clear if one or

two digits are to be driven, and set if three or four digits

are to be driven (Table 21).

Intensity Registers

Display brightness is controlled digitally by four pulse-

width modulators, one for each display digit. Each digit

is controlled by a nibble of one of the two intensity reg-

isters, Intensity10 and Intensity32. The modulator

scales the average segment current in 16 steps from a

maximum of 15/16 down to 1/16 of the peak current.

The minimum interdigit blanking time is therefore 1/16

of a cycle. The maximum duty cycle is 15/16 (Tables 23

and 24).

No-Op Register

A write to the No-Op register is ignored.

Segment Current

REGISTER DATA

FONT

CHARACTER

ADDRESS

CODE (HEX)

REGISTER

DATA (HEX)

D7

D6

D5

D4

D3

D2

D1

D0

RAM00

0x05

0x80

1

0

0

0

0

0

0

0

RAM01

0x05

0x85

1

0

0

0

0

1

0

1

RAM02

0x05

0x8A

1

0

0

0

1

0

1

0

RAM03

0x05

0x8F

1

0

0

0

1

1

1

1

RAM04

0x05

0x94

1

0

0

1

0

1

0

0

RAM05

0x05

0x99

1

0

0

1

1

0

0

1

RAM06

0x05

0x9E

1

0

0

1

1

1

1

0

RAM07

0x05

0xA3

1

0

1

0

0

0

1

1

RAM08

0x05

0xA8

1

0

1

0

1

0

0

0

RAM09

0x05

0xAD

1

0

1

0

1

1

0

1

RAM10

0x05

0xB2

1

0

1

1

0

0

1

0

RAM11

0x05

0xB7

1

0

1

1

0

1

1

1

RAM12

0x05

0xBC

1

0

1

1

1

1

0

0

RAM13

0x05

0xC1

1

1

0

0

0

0

0

1

RAM14

0x05

0xC6

1

1

0

0

0

1

1

0

RAM15

0x05

0xCB

1

1

0

0

1

0

1

1

RAM16

0x05

0xD0

1

1

0

1

0

0

0

0

RAM17

0x05

0xD5

1

1

0

1

0

1

0

1

RAM18

0x05

0xDA

1

1

0

1

1

0

1

0

RAM19

0x05

0xDF

1

1

0

1

1

1

1

1

RAM20

0x05

0xE4

1

1

1

0

0

1

0

0

RAM21

0x05

0xE9

1

1

1

0

1

0

0

1

RAM22

0x05

0xEE

1

1

1

0

1

1

1

0

RAM23

0x05

0xF3

1

1

1

1

0

0

1

1

Table 18. User-Definable Font Pointer Base Address Table