ADE7923 datasheet(69/125 Pages) AD

69 / 125 page

Data Sheet

ADE7978/ADE7933/ADE7932/ADE7923

Rev. D | Page 69 of 125

INTEGRATION TIME UNDER STEADY LOAD

The discrete time sample period (T) for the accumulation

registers is 976.5625 ns (1.024 MHz frequency). With full-scale

pure sinusoidal signals on the analog inputs, the average word

value representing the apparent power is PMAX. If the VATHR

threshold register is set to 3 (its minimum recommended value),

the first stage accumulator generates a pulse that is added to the

xVAHR registers at intervals of

5683

024

PMAX

The maximum value that can be stored in the xVAHR accumu-

lation register before it overflows is 231 − 1 or 0x7FFFFFFF. The

integration time is calculated as follows:

Time = 0x7FFFFFFF × 14.5683 µs = 8 hr, 41 min, 25 sec

(47)

ENERGY ACCUMULATION MODE

The apparent power is accumulated in each 32-bit VA-hour

accumulation register (AVAHR, BVAHR, and CVAHR)

according to the configuration of Bits[5:4] (CONSEL[1:0] bits)

in the ACCMODE register (see Table 28).

Table 28. Inputs to VA-Hour Accumulation Registers

CONSEL[1:0] AVAHR

BVAHR

CVAHR

AVRMS × AIRMS BVRMS × BIRMS CVRMS × CIRMS

VB = VA − VC1

Reserved

AVRMS × AIRMS BVRMS × BIRMS CVRMS × CIRMS

VB = −VA

1 See the BWATTHR and BFWATTHR Accumulation Register in 3-Phase, 3-Wire

Configurations section.

BWATTHR and BFWATTHR Accumulation Register in

3-Phase, 3-Wire Configurations

In a 3-phase, 3-wire configuration (CONSEL[1:0] = 01), the

ADE7978 computes the rms value of the line voltage between

Phase A and Phase C and stores the result in the BVRMS register

(see the Voltage RMS in Delta Configurations section). The

Phase B current value provided after the HPF is 0; therefore,

the powers associated with Phase B are 0.

To avoid any errors in the frequency output pins (CF1, CF2, or

CF3) related to the powers associated with Phase B, disable the

contribution of Phase B to the energy-to-frequency converters

by setting the TERMSEL1[1], TERMSEL2[1], or TERMSEL3[1]

bit to 0 in the COMPMODE register (Address 0xE60E). For more

information, see the Energy-to-Frequency Conversion section.

LINE CYCLE APPARENT ENERGY ACCUMULATION

MODE

In line cycle energy accumulation mode, the energy accumulation

is synchronized to the voltage channel zero crossings, allowing

apparent energy to be accumulated over an integral number of

half line cycles. In line cycle energy accumulation mode, the

ADE7978 transfers the apparent energy accumulated in the

32-bit internal accumulation registers to the xVAHR registers

after an integral number of line cycles (see Figure 90). The

number of half line cycles is specified in the LINECYC register

(Address 0xE60C).

ZERO-

CROSSING

DETECTION

(PHASE A)

ZERO-

CROSSING

DETECTION

(PHASE B)

CALIBRATION

CONTROL

ZERO-

CROSSING

DETECTION

(PHASE C)

LINECYC[15:0]

ZXSEL[0] IN

LCYCMODE[7:0]

ZXSEL[1] IN

LCYCMODE[7:0]

ZXSEL[2] IN

LCYCMODE[7:0]

INTERNAL

ACCUMULATOR

THRESHOLD

APGAIN

VATHR

27 26

32-BIT REGISTER

AVAHR[31:0]

AIRMS

AVRMS

Figure 90. Line Cycle Apparent Energy Accumulation Mode

The line cycle apparent energy accumulation mode is activated by

setting Bit 2 (LVA) in the LCYCMODE register (Address 0xE702).

The apparent energy accumulated over an integer number of half

line cycles (or zero crossings) is written to the xVAHR accumula-

tion registers after the number of half line cycles specified in the

LINECYC register is detected. When using the line cycle accumu-

lation mode, set Bit 6 (RSTREAD) of the LCYCMODE register

to Logic 0 because a read with reset of the xVAHR registers

outside the LINECYC period resets the energy accumulation.

Phase A, Phase B, and Phase C zero crossings are included

when counting the number of half line cycles by setting

Bits[5:3] (ZXSEL[x]) in the LCYCMODE register. Any combi-

nation of zero crossings from all three phases can be used to

count the zero crossings. Select only one phase at a time for

inclusion in the count of zero crossings during calibration.

For more information about setting the LINECYC register and

Bit 5 (LENERGY) in the MASK0 register associated with the

line cycle accumulation mode, see the Line Cycle Active Energy

Accumulation Mode section.

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