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ADIN1100CCPZ-R7 数据表(PDF) 69 Page - Analog Devices |
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ADIN1100CCPZ-R7 数据表(HTML) 69 Page - Analog Devices |
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69 / 78 page  Data Sheet ADIN1100 ETHERNET CLAUSE 45 REGISTER DETAILS analog.com Rev. 0 | 69 of 78 Table 111. Bit Descriptions for MMD2_STATUS Bits Bit Name Description Reset Access [15:14] MMD2_STATUS Vendor Specific MMD 2 Status. 0x2 R 10: device responding at this address. 11: no device responding at this address. 01: no device responding at this address. 00: no device responding at this address. [13:0] RESERVED Reserved. 0x0 R PHY SUBSYSTEM INTERRUPT STATUS REGISTER Device Address: 0x1F; Register Address: 0x0011, Reset: 0x0000, Name: PHY_SUBSYS_IRQ_STATUS This address can be read to check which interrupt events have occurred since the last time it was read. Each bit goes high when the associated event occurs and then latches high until it is unlatched by reading. The bits of PHY_SUBSYS_IRQ_STATUS go high even when the associated bits in PHY_SUBSYS_IRQ_MASK are not set. A reserved interrupt being triggered indicates a fatal error in the system. Table 112. Bit Descriptions for PHY_SUBSYS_IRQ_STATUS Bits Bit Name Description Reset Access 15 RESERVED Reserved. 0x0 R LH 14 MAC_IF_FC_FG_IRQ_LH MAC Interface Frame Checker/Generator Interrupt. 0x0 R LH 13 MAC_IF_EBUF_ERR_IRQ_LH MAC Interface Buffers Overflow/Underflow Interrupt. 0x0 R LH 12 RESERVED Reserved. 0x0 R LH 11 AN_STAT_CHNG_IRQ_LH Autonegotiation Status Change Interrupt. 0x0 R LH [10:2] RESERVED Reserved. 0x0 R LH 1 LINK_STAT_CHNG_LH Link Status Change. 0x0 R LH 0 RESERVED Reserved. 0x0 R LH PHY SUBSYSTEM INTERRUPT MASK REGISTER Device Address: 0x1F; Register Address: 0x0021, Reset: 0x2402, Name: PHY_SUBSYS_IRQ_MASK Controls whether or not the interrupt signal is asserted in response to various events. Table 113. Bit Descriptions for PHY_SUBSYS_IRQ_MASK Bits Bit Name Description Reset Access 15 RESERVED Reserved. 0x0 R/W SC 14 MAC_IF_FC_FG_IRQ_EN Enable MAC Interface Frame Checker/Generator Interrupt. 0x0 R/W 13 MAC_IF_EBUF_ERR_IRQ_EN Enable MAC Interface Buffers Overflow/Underflow Interrupt. 0x1 R/W 12 RESERVED Reserved. 0x0 R/W 11 AN_STAT_CHNG_IRQ_EN Enable Autonegotiation Status Change Interrupt. 0x0 R/W [10:2] RESERVED Reserved. 0x100 R/W 1 LINK_STAT_CHNG_IRQ_EN Enable Link Status Change Interrupt. 0x1 R/W 0 RESERVED Reserved. 0x0 R/W FRAME CHECKER ENABLE REGISTER Device Address: 0x1F; Register Address: 0x8001, Reset: 0x0001, Name: FC_EN This register is used to enable the frame checker. The frame checker analyzes the received frames from either the MAC interface or the PHY (see the FC_TX_SEL register) to report the number of frames received, CRC errors, and various other frame errors. The frame checker frame and error counter registers count these events. |
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