3

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PS9060A

08/23/11

PI3VDP411LSR

Dual Mode DisplayPort™ to DVI/HDMI™ Electrical Bridge (Level Shifter)

Pin

Name

I/O Type

Descriptions

1, 5, 12, 18, 24, 27,

31, 36, 37, 43

GND

POWER

GROUND

2, 11, 15, 21, 26, 33,

40, 46

POWER

POWER, 3.3V ±10%

3

SR0

I

Slew Rate Control. Acceptable connections to SR0 pin are: resistor

to 3.3V or short to GND. (internal 200KΩ pull-LOW)

4

SR1

I

Slew Rate Control. Acceptable connections to SR1 pin are: resistor

to 3.3V or short to GND. (internal 200KΩ pull-LOW)

6, 10, 34, 35

NC

O

No Connect

7

HPD_SOURCE

O

HPD_SOURCE: 0V to 3.3V (nominal) output signal. HPD_Sink

input can be as high as 5V and then HPD_Source will output no

higher than 3.3V.

8

SDA_SOURCE

I/O

3.3V DDC Data I/O. Pulled up by external termination to 3.3V.

Connected to SDA_SINK through voltage limiting integrated

NMOS passgate.

9

SCL_SOURCE

I/O

3.3V DDC Data I/O. Pulled up by external termination to 3.3V.

Connected to SCL_SINK through voltage-limiting integrated

NMOS passgate

13

OUT_D4+

O

HDMI 1.3 compliant TMDS output. OUT_D4+ makes a differential

output signal with OUT_D4-.

14

OUT_D4-

O

HDMI 1.3 compliant TMDS output. OUT_D4- makes a differential

output signal with OUT_D4+

16

OUT_D3+

O

HDMI 1.3 compliant TMDS output. OUT_D3+ makes a differential

output signal with OUT_D3-.

17

OUT_D3-

O

HDMI 1.3 compliant TMDS output. OUT_D3- makes a differential

output signal with OUT_D3+

19

OUT_D2+

O

HDMI 1.3 compliant TMDS output. OUT_D2+ makes a differential

output signal with OUT_D2-.

20

OUT_D2-

O

HDMI 1.3 compliant TMDS output. OUT_D2- makes a differential

output signal with OUT_D2+

22

OUT_D1+

O

HDMI 1.3 compliant TMDS output. OUT_D1+ makes a differential

output signal with OUT_D1-.

23

OUT_D1-

O

HDMI 1.3 compliant TMDS output. OUT_D1- makes a differential

output signal with OUT_D1+

25

OE#

I

Enable for IN_Dx to OUT_Dx level shifter path.

OE#

IN_D Termination

OUT_D Outputs

1

> 100KΩ

High-Z

0

50Ω

Active

28

SCL_SINK

I/O

5V DDC Clock I/O. Pulled up by external termination to 5V.

Connected to SCL_SOURCE through voltage limiting integrated

NMOS passgate.

11-0084