71M6543HT datasheet(58/75 Pages) MAXIM

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Energy Meter ICs

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Table 13. I/O RAM Locations in Alphabetical Order (continued)

NAME

LOCATION RSTWK DIR

DESCRIPTION

LCD_VMODE[1:0]

2401[7:6] 00 00 R/W

SpecifieshowVLCD is generated.

LCD_VMODE

DESCRIPTION

External VLCD

LCD DAC enabled

No DAC. VLCD = V3P3L.

LCD_Y

2400[2]

– R/W LCDBlinkFrequency(ignoredifblinkisdisabled).

1 = 1 Hz, 0 = 0.5 Hz

MPU_DIV[2:0]

2200[2:0]

0 R/W

MPU clock rate is:

MPU Rate = MCK Rate x 2-(2+MPU_DIV[2:0]).

The maximum value for MPU_DIV[2:0] is 4. Based on the default values of the PLL_FAST bit and MPU_DIV[2:0],

the power up MPU rate is 6.29MHz/4 = 1.5725MHz. The minimum MPU clock rate is 38.4kHz when PLL_FAS T =

MUX2_SEL[3:0]

2104[3:0]

0 R/W Selects which ADC input is to be converted during time slot 2.

MUX3_SEL[3:0]

2104[7:4]

0 R/W Selects which ADC input is to be converted during time slot 3.

MUX4_SEL[3:0]

2103[3:0]

0 R/W Selects which ADC input is to be converted during time slot 4.

MUX5_SEL[3:0]

2103[7:4]

0 R/W Selects which ADC input is to be converted during time slot 5.

MUX6_SEL[3:0]

2102[3:0]

0 R/W Selects which ADC input is to be converted during time slot 6.

MUX7_SEL[3:0]

2102[7:4]

0 R/W Selects which ADC input is to be converted during time slot 7.

MUX8_SEL[3:0]

2101[3:0]

0 R/W Selects which ADC input is to be converted during time slot 8.

MUX9_SEL[3:0]

2101[7:4]

0 R/W Selects which ADC input is to be converted during time slot 9.

MUX10_SEL[3:0]

2100[3:0]

0 R/W Selects which ADC input is to be converted during time slot 10.

MUX_DIV[3:0]

2100[7:4]

0 R/W MUX_DIV[3:0] is the number of ADC time slots in each MUX frame. The maximum number of time slots is 11.

OPT_BB

2457[0]

– R/W ConfigurestheinputoftheopticalporttobeaDIOpintoallowittobebit-banged.Inthiscase,DIO5becomesa

third high speed UART.

OPT_FDC[1:0]

2457[5:4]

– R/W

Selects OPT_TX modulation duty cycle.

OPT_FDC

FUNCTION

50% low

25% low

12.5% low

6.25% low

OPT_RXDIS

2457[2]

– R/W

OPT_RXcanbeconfiguredasaninputtotheopticalUARTorasSEGDIO55.

OPT_RXDIS = 0 and LCD_MAP[55] = 0: OPT_RX

OPT_RXDIS = 1 and LCD_MAP[55] = 0: DIO55

OPT_RXDIS = 0 and LCD_MAP[55] = 1: SEG55

OPT_RXDIS = 1 and LCD_MAP[55] = 1: SEG55

OPT_RXINV

2457[1]

– R/W Inverts result from OPT_RX comparator when 1. Affects only the UART input. Has no effect when OPT_RX is used

as a DIO input.

OPT_TXE [1:0]

2456[3:2] 00 – R/W

ConfigurestheOPT_TXoutputpin.

If LCD_MAP[51] = 0:

00 = DIO51, 01 = OPT_TX, 10 = WPULSE, 11 = VARPULSE

If LCD_MAP[51] = 1:

xx = SEG51

OPT_TXINV

2456[0]

– R/W Invert OPT_TX when 1. This inversion occurs before modulation.

OPT_TXMOD

2456[1]

– R/W Enables modulation of OPT_TX. When OPT_TXMOD is set, OPT_TX is modulated when it would otherwise have

been zero. The modulation is applied after any inversion caused by OPT_TXINV.

OSC_COMP

28A0[5]

– R/W Enables the automatic update of the PQ RTC compensation value every time the temperature is measured.

OUT_SQ[1:0]

2200[7:6]

0 R/W

DefinesthesquarewaveoutputonSEGDIO15(ifOUT_SQE=1)

00 – Off

01 – 3.2768MHz

10 – 4.9152MHz

11 – 9.83MHz

OUT_SQE

2458[4]

0 R/W EnablesthesquarewaveoutputonSEGDIO15.

PB_STATE

SFR F8[0]

0 R The de-bounced state of the PB pin.

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