71M6543HT-IGTSLASHF datasheet(28/75 Pages) MAXIM

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Table 4. Memory Map

*Memory size depends on IC. See the On-Chip Resources section for details.

• MOVX A,@Ri: The contents of R0 or R1 in the current

with the eight high-order bits specified by the PDATA

SFR. This method allows the user paged access (256

pages of 256 bytes each) to all ranges of the external

data RAM.

• MOVX A,@DPTR: The data pointer generates a 16-bit

address. This form is faster and more efficient when

accessing very large data arrays (up to 64KB) since no

additional instructions are needed to set up the eight

high ordered bits of the address.

It is possible to mix the two MOVX types. This provides

the user with four separate data pointers, two with direct

access and two with paged access, to the entire external

memory range.

Dual Data Pointer

The Dual Data Pointer accelerates the block moves of

data. The standard DPTR is a 16-bit register that is used

to address external memory or peripherals. In the 80515

core, the standard data pointer is called DPTR, the sec-

ond data pointer is called DPTR1. The data pointer select

bit, located in the LSB of the DPS register, chooses the

active pointer. DPTR is selected when DPS[0] = 0 and

DPTR1 is selected when DPS[0] = 1.

The user switches between pointers by toggling the LSB

of the DPS register. The values in the data pointers are

not affected by the LSB of the DPS register. All DPTR

related instructions use the currently selected DPTR for

any activity.

An alternative data pointer is available in the form of the

PDATA register (SFR 0xBF), sometimes referred to as

USR2). It defines the high byte of a 16-bit address when

reading or writing XDATA with the instruction MOVX A,@

Ri or MOVX @Ri,A.

Internal Data Memory Map and Access

The Internal data memory provides 256 bytes (0x00 to

0xFF) of data memory. The internal data memory address

is always 1 byte wide.

The Special Function Registers (SFR) occupy the upper

128 bytes. The SFR area of internal data memory is

available

only by direct addressing. Indirect address-

ing of this area accesses the upper 128 bytes of Internal

RAM. The lower 128 bytes contain working registers and

bit addressable memory. The lower 32 bytes form four

banks of eight registers (R0-R7). Two bits on the program

memory status word (PSW, SFR 0xD0) select which bank

is in use. The next 16 bytes form a block of bit address-

able memory space at addresses 0x00-0x7F. All of the

bytes in the lower 128 bytes are accessible through direct

or indirect addressing.

Table 5. Internal Data Memory Map

ADDRESS

(hex)

MEMORY

TECHNOLOGY

MEMORY

TYPE

NAME

TYPICAL USAGE

MEMORY SIZE

(BYTES)

0000-FFFF

(64K)

0000-1FFFF

(128K)

Flash Memory

Nonvolatile

Program memory for MPU and

MPU program and

nonvolatile data

128/64K*

CE program (on 1KB

boundary)

3K max

0000-0BFF

Static RAM

Volatile

External RAM (XRAM)

Shared by CE and MPU

5K*

2000-27FF

Static RAM

Volatile

ConfigurationRAM(I/ORAM)

Hardware control

2800-287F

Static RAM

Nonvolatile

(battery)

ConfigurationRAM(I/ORAM)

Battery-buffered memory

128

0000-00FF

Static RAM

Volatile

Internal RAM

Part of 80515 Core

256

ADDRESS RANGE

DIRECT ADDRESSING

INDIRECT ADDRESSING

0x80

0xFF

Special Function Registers (SFRs)

RAM

0x30

0x7F

Byte addressable area

0x20

0x2F

Bit addressable area

0x00

0x1F

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