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71M6543HT-IGT/F 数据表(PDF) 32 Page - Maxim Integrated Products |
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71M6543HT-IGT/F 数据表(HTML) 32 Page - Maxim Integrated Products |
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32 / 75 page  Maxim Integrated │ 32 71M6543FT/71M6543HT/ 71M6543GT/71M6543GHT Energy Meter ICs www.maximintegrated.com Table 10. Flash Banks resides. The address of the CE program is 0bXXXX XX00 0000 0000, where XXXX XX represents one of the 64 1KB pages at which the CE program begins. Flash memory can be accessed by the MPU and the CE for reading, and by the SPI interface for reading or writing. The program memory of the 71M6543GT/71M6543GHT consists of a fixed lower bank area of 32 kB addressable at 0x0000 to 0x7FFF plus an upper bank area of 32 kB, addressable at 0x8000 to 0xFFFF. The upper bank area is banked using the I/O RAM FLSH_BANK register as follows. Note that when FLSH_BANK[1:0] = 00, the upper bank area is the same as the lower bank area (Table 10). The flash memory page address register FLSH_ PGADR[6:0] (SFR B7[7:1]) points to an address in the 71M6543GT/71M6543GHT program address space. This address in the 71M6543GT/71M6543GHT program address space can refer to different flash memory address- es, depending on the setting of the FLSH_BANK[1:0] bits. The CE location register (CE_LCTN[6:0]), on the other hand, points directly to an address in the flash memory and is not affected by the FLSH_BANK[1:0] bits. When the SECURE bit (SFR B2[6]) is set to a 1, page erase of certain flash memory pages is blocked. These pages are page 0 (flash memory address range 0x00000 –0x003FF) and all pages between the start of the CE program (CE_LCTN[6:0]) and flash memory address 0x1FFFF. While operating in SPI flash mode (SFM), SPI single- byte transactions are used to write to FLSH_BANK[1:0]. During a SPI single-byte transaction, SPI_CMD[1:0] overwrites the contents of FLSH_BANK[1:0]. This allows access to the entire 128KB flash memory while operating in SFM on the 71M6543GT/71M6543GHT. MPU/CE RAM The 71M6543FT/HT/GT/GHT includes 5KB of static RAM memory on-chip (XRAM) plus 256 bytes of internal RAM in the MPU core. The static RAM is used for data storage for both MPU and CE operations. I/O RAM The I/O RAM can be seen as a series of hardware reg- isters that control basic hardware functions. I/O RAM address space starts at 0x2000. The 71M6543FT/HT/GT/GHT includes 128 bytes NV RAM memory on-chip in the I/O RAM address space (addresses 0x2800 to 0x287F). This memory section is supported by the voltage applied at VBAT_RTC and the data in it are preserved in BRN, LCD, and SLP modes as long as the voltage at VBAT_RTC is within specification. Crystal Oscillator The oscillator drives a standard 32.768kHz tuning-fork crystal. This type of crystal is accurate and does not require a high-current oscillator circuit. The oscillator power dissipation is very low to maximize the lifetime of the VBAT_RTC battery. Oscillator calibration can improve the accuracy of both the RTC and metering. PLL Timing for the device is derived from the 32,768Hz crystal oscillator. The oscillator output is routed to a phase-locked loop (PLL). The PLL multiplies the crystal frequency by 600toproduceastable19.6608MHzclockfrequency.This is the master clock (MCK), and all on-chip timing, except for the RTC clock, is derived from MCK. The master clock can operate at either 19.66MHz or 6.29MHz depending on the PLL_FAST bit. The MPU clockfrequencyCKMPUisdeterminedbyanotherdivider controlled by the I/O RAM control field MPU_DIV[2:0] and can be set to MCK x 2-(MPU_DIV+2) , where MPU_DIV[2:0] may vary from 0 to 4. The 71M654xT VV3P3SYS supply currentisreducedbyreducingtheMPUclockfrequency. When the ICE_E pin is high, the circuit also generates the 9.83MHz clock for use by the emulator. The two general-purpose counter/timers contained in the MPU are clocked by CKMPU. The PLL is only turned off in SLP mode. FLSH_BANK[1:0] ADDRESS RANGE FOR LOWER BANK (0x0000–0x7FFF) ADDRESS RANGE FOR UPPER BANK (0x8000–0x7FFF) 00 0x0000–0x7FFF 0x0000–0x7FFF 01 0x0000–0x7FFF 0x8000–0x7FFF 10 0x0000–0x7FFF 0x10000–0x17FFFF 11 0x0000–0x7FFF 0x18000–0x1FFFF |
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