ADP1621ARMZ-R7 datasheet(14/32 Pages) AD

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ADP1621

Data Sheet

Rev. D | Page 14 of 32

APPLICATION INFORMATION: BOOST CONVERTER

In this section, an analysis of a boost converter is presented,

along with guidelines for component selection. A typical boost-

converter application circuit is shown in Figure 1.

ADIsimPower DESIGN TOOL

The ADP1621 is supported by ADIsimPower design tool set.

ADIsimPower is a collection of tools that produce complete

power designs optimized for a specific design goal. The tools

enable the user to generate a full schematic, bill of materials,

and calculate performance in minutes. ADIsimPower can

optimize designs for cost, area, efficiency, and device count

while taking into consideration the operating conditions and

limitations of the IC and all real external components. For

more information about ADIsimPower design tools, refer to

www.analog.com/ADIsimPower. The tool set is available from

this website, and users can also request an unpopulated board

through the tool.

DUTY CYCLE

To determine the worst-case inductor current ripple, output

voltage ripple, and slope-compensation factor, it is first

necessary to determine the system duty cycle. The duty cycle in

continuous conduction mode (CCM) is calculated by the following

equation:

OUT

−

(1)

where:

VOUT is the desired output voltage.

VIN is the input voltage.

VD is the forward-voltage drop of the diode. A typical Schottky

diode has a forward-voltage drop of 0.5 V.

The GATE minimum on and off times determine the minimum

and maximum duty cycles, respectively. The minimum on and off

times are typically 180 ns and 190 ns, respectively. The minimum

and maximum duty cycles are given by the following equations:

MIN

(2)

)

(

MIN

OFF

MIN

OFF

MAX

−

(3)

where:

DMIN is the minimum duty cycle.

DMAX is the maximum duty cycle.

tON,MIN is the minimum on time.

tOFF,MIN is the minimum off time.

tSW is the switching period.

fSW is the switching frequency.

Note that when the converter tries to operate at a duty cycle

lower than DMIN, pulse-skipping modulation occurs to maintain

the output voltage regulation (see the Light Load Operation

section).

SETTING THE OUTPUT VOLTAGE

The output voltage is set through a voltage divider from the output

voltage to the FB input. The feedback resistor ratio sets the output

voltage of the system. The regulation voltage at FB is 1.215 V. The

output voltage is given by the following equation (see Figure 1):











 +

VOUT

215

(4)

The input bias current into FB is 25 nA typical, 70 nA maximum.

For a 0.1% degradation in regulation voltage and with 70 nA

bias current, R2 must be less than 18 kΩ, which results in 68 µA

of divider current. Choose the value of R1 to set the output

voltage. Using higher values for R2 results in reduced output

voltage accuracy due to the input bias current at the FB pin,

whereas lower values cause increased quiescent current

consumption.

INDUCTOR CURRENT RIPPLE

Choose a peak-to-peak inductor ripple current between 20%

and 40% of the average inductor current. A good starting point

for a design is to choose the peak-to-peak ripple current to be

30% of 1/(1 − D) times the maximum load current:

MAX

LOAD

−

∆

(5)

where:

ΔIL is the peak-to-peak inductor ripple current.

ILOAD,MAX is the maximum load current required by the application.

INDUCTOR SELECTION

The inductor value choice is important because it dictates the

inductor current ripple and therefore the voltage ripple at the

output.

The average inductor current, IL,AVE, is given by the following

equation:

LOAD

AVE

−

(6)

and the peak-to-peak inductor ripple current is inversely

proportional to the inductor value:

∆

(7)

where:

fSW is the switching frequency.

L is the inductor value.

Assuming continuous conduction mode (CCM) operation, the

peak inductor current is given by the following equation:

LOAD

−

∆

−

(8)

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