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ADP2503ACPZ-3.3-R7 数据表(PDF) 4 Page - Analog Devices |
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ADP2503ACPZ-3.3-R7 数据表(HTML) 4 Page - Analog Devices |
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4 / 16 page ![]() ADP2503/ADP2504 Data Sheet Rev. D | Page 4 of 16 ABSOLUTE MAXIMUM RATINGS Table 2. Parameter Rating PVIN, VIN, SW1, SW2, VOUT, SYNC, EN, FB −0.3 V to +6 V PGND to AGND −0.3 V to 0.3 V Operating Ambient Temperature Range −40°C to +125°C Operating Junction Temperature Range −40°C to +125°C Storage Temperature Range −65°C to +150°C Soldering Conditions JEDEC J-STD-020 ESD Human Body Model ±2000 V ESD Charged Device Model ±1500 V ESD Machine Model ±100 V Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the product. This is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability. THERMAL DATA Absolute maximum ratings apply individually only, not in combination. The ADP2503/ADP2504 can be damaged when the junction temperature limits are exceeded. Monitoring ambient tempera- ture (TA) does not guarantee that the junction temperature (TJ) is within the specified temperature limits. In applications with high power dissipation and poor thermal resistance, the maximum ambient temperature may have to be derated. In applications with moderate power dissipation and low PCB thermal resis- tance, the maximum ambient temperature can exceed the maximum limit as long as the junction temperature is within specification limits. TJ of the device is dependent on TA, the power dissipation (PD) of the device, and the junction-to- ambient thermal resistance (θJA) of the package. Maximum TJ is calculated from TA and PD using the following formula: TJ = TA + (PD × θJA) θJA of the package is based on modeling and calculation using a 4-layer board. The junction-to-ambient thermal resistance is highly dependent on the application and board layout. In applica- tions where high maximum power dissipation exists, close attention to thermal board design is required. The value of θJA may vary, depending on PCB material, layout, and environmental conditions. The specified values of θJA are based on a 4-layer, 4 inch × 3 inch circuit board. Refer to JEDEC JESD 51-9 for detailed information on the board construction. THERMAL RESISTANCE θJA are specified for the worst-case conditions, that is, a device soldered in a circuit board for surface-mount packages. Table 3. Package Type JA Unit 10-Lead LFCSP (QFN) 84 °C/W ESD CAUTION |
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