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ADP2450ACPZ-5-R7 数据表(PDF) 10 Page - Analog Devices |
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ADP2450ACPZ-5-R7 数据表(HTML) 10 Page - Analog Devices |
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10 / 40 page  ADP2450 Data Sheet Rev. B | Page 10 of 40 PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS 24 FB2 23 RSTO 22 GAIN0 21 GAIN1 20 EOUT5 19 EIN5_N 18 EIN5_P 17 VCOM 1 2 3 4 5 6 7 8 PGND1 GATE TRG VTRP VREG GND AVDD EIN1 ADP2450 TOP VIEW (Not to Scale) NOTES 1. EXPOSED PAD. SOLDER THE EXPOSED PAD TO AN EXTERNAL GND PLANE. Figure 3. 32-Lead LFCSP Package Pin Configuration (Top View) 48 47 46 45 44 43 42 41 40 39 38 37 35 34 33 30 31 32 36 29 28 27 25 26 2 3 4 7 6 5 1 8 9 10 12 11 NOTES 1. NIC = NOT INTERNALLY CONNECTED. LEAVE THIS PIN OPEN. 13 14 15 16 17 18 19 20 21 22 23 24 ADP2450 (Not to Scale) TOP VIEW FB2 RSTO GAIN0 NIC NIC GAIN1 NIC EOUT5 EIN5_N EIN5_P NIC VCOM PGND1 GATE TRG VTRPL VTRP NIC NIC VREG GND AVDD NIC EIN1 Figure 4. 48-Lead LQFP Package Pin Configuration (Top View) Table 7. Pin Function Descriptions Pin No. Mnemonic Description LFCSP 32-Lead LQFP 48-Lead 1 2 PGND1 Boost Shunt Driver and Actuator Driver Ground. 2 3 GATE Actuator Driver. This pin drives the silicon controlled rectifier (SCR), field-effect transistor (FET), or transistor. 3 4 TRG Actuator Trigger Signal. This signal comes from the microcontroller unit (MCU). 4 6 VTRP Analog Trip High Threshold Setting. Connect a resistor between this pin and ground to set the analog trip high threshold. 7 VTRPL Analog Trip Low Threshold Setting. Connect a resistor between this pin and ground to set the analog trip low threshold. 5 8 VREG Internal 5 V Regulator Output. The IC control circuits are powered from this voltage. Place a 1 μF ceramic capacitor between VREG and GND. 6 9 GND Analog Ground. Connect this pin to the ground plane. 7 10 AVDD Power Supply for the Amplifier Block. 8 11 EIN1 Input of the Programmable Gain Amplifier 1. 9 13 EOUT1 Output of the Programmable Gain Amplifier 1. 10 15 EIN2 Input of the Programmable Gain Amplifier 2. 11 16 EOUT2 Output of the Programmable Gain Amplifier 2. 12 18 EIN3 Input of the Programmable Gain Amplifier 3. 13 19 EOUT3 Output of the Programmable Gain Amplifier 3. 14 21 EIN4 Input of the Programmable Gain Amplifier 4. 15 22 EOUT4 Output of the Programmable Gain Amplifier 4. 16 23 RCOM External Resistance Compensation for Programmable Gain Amplifier 1 to Amplifier 4. 17 26 VCOM Setting for the Output Common Voltage of the Programmable Gain Amplifiers. This pin is connected to an external reference voltage. 18 27 EIN5_P Positive Input of Amplifier 5. 19 28 EIN5_N Negative Input of Amplifier 5. 20 29 EOUT5 Output of the Amplifier 5. 21 32 GAIN1 Gain Setting for Programmable Gain Amplifier 1 to Amplifier 4. This pin is combined with GAIN0 to set the gain of the amplifier. |
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