TDA7575PD

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interface, consisting of the two lines SDA and SCL (pull-up resistors to positive supply voltage must be connected).

Data Validity

As shown by fig. 1, the data on the SDA line must be stable during the high period of the clock.

The HIGH and LOW state of the data line can only change when the clock signal on the SCL line is LOW.

Start and Stop Conditions

As shown by fig. 2 a start condition is a HIGH to LOW transition of the SDA line while SCL is HIGH.

The stop condition is a LOW to HIGH transition of the SDA line while SCL is HIGH.

Byte Format

Every byte transferred to the SDA line must contain 8 bits. Each byte must be followed by an acknowledge bit.

The MSB is transferred first.

Acknowledge

The transmitter* puts a resistive HIGH level on the SDA line during the acknowledge clock pulse (see fig.3). The

receiver** the acknowledges has to pull-down (LOW) the SDA line during the acknowledge clock pulse, so that

the SDAline is stable LOW during this clock pulse.

* Transmitter

=master (

µP) when it writes an address to the TDA7575PD

= slave (TDA7575PD) when the

µP reads a data byte from TDA7575PD

** Receiver

= slave (TDA7575PD) when the

µP writes an address to the TDA7575PD

=master (

µP) when it reads a data byte from TDA7575PD

Offset Detection

Power Amplifier in play condition

AC Input signals = 0

±1.5

±2

±2.5

V

Clock Frequency

400

KHz

Input Low Voltage

1.5

V

Input High Voltage

2.3

V

Symbol

Parameter

Test Condition

Min.

Typ.

Max.

Unit

ELECTRICAL CHARACTERISTCS: (continued)