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2022 Microchip Technology Inc. and its subsidiaries

DS20006672A-page 5

PL133-97

2.0

PIN DESCRIPTIONS

FIGURE 2-1:

Pin Configuration, 16-Lead QFN Package.

The descriptions of the pins are listed in Table 2-1.

TABLE 2-1:

PIN FUNCTION TABLE

Pin Number P8in Name

Type

Description

15

REF

I

Input reference frequency

1

CLK1

O

Buffered clock output

4

CLK2

O

Buffered clock output

5

CLK3

O

Buffered clock output

8

CLK4

O

Buffered clock output

9

CLK5

O

Buffered clock output

12

CLK6

O

Buffered clock output

13

CLK7

O

Buffered clock output

14

CLK8

O

Buffered clock output, free running, does not disable with OE

16

CLK9

O

Buffered clock output

2, 11

VDD

P

VDD connection

3, 7, 10

GND

P

GND connection

6

OE

I

Output enable control input with 130 kΩ pull-up

ePAD

—

—

Center Pad for thermal relief. Connect to GND

CLK4

OE

CLK3

GND

CLK8

CLK7

REF

12

3

4

8

7

6

5

12

11

10

9

13

14

15

16

CLK9