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2022 Microchip Technology Inc. and its subsidiaries

DS20006672A-page 1

PL133-97

Features

• 1:9 LVCMOS Output Fanout Buffer from DC

to150 MHz

• Low Additive Phase Jitter of 60 fs RMS

• 8 mA Output Drive Strength

• Low Power Consumption for Portable

Applications

• Low Input-Output Delay

• Output-Output Skew <250 ps

• 2.5V to 3.3V, ±10% Operation

• 1.8V ±5% Operation up to 67 MHz

• Operating Temperature Range:

- Commercial: 0°C to +70°C

- Industrial: –40°C to +85°C

• Available in 16-Pin QFN Package

General Description

The PL133-97 is an advanced fanout buffer designed

for high performance, low-power, small form factor

applications. The PL133-97 accepts a reference clock

input from DC to 150 MHz and provides nine outputs of

the same frequency.

The PL133-97 is offered in a small 3 mm x 3 mm

QFN-16L package and it offers the best phase noise,

additive jitter performance, and lowest power

consumption of any comparable IC.

The PL133-97 outputs can be disabled to a high

impedance (tri-state) by pulling low the OE pin. When

the OE pin is high, the outputs are enabled and follow

the REF input signal. When the OE pin is left open, a

pull-up resistor on the chip will default the OE pin to

logic 1 so the outputs are enabled.

CLK8 is a free running output that remains enabled

when the OE pin is pulled low.

Functional Block Diagram

REF

CLK1

CLK2

CLK3

CLK4

CLK5

CLK6

OE

CLK8

CLK7

CLK9

Low-Power DC to 150 MHz 1:9 Fanout Buffer IC