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STLC4420A 数据表(PDF) 6 Page - STMicroelectronics |
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STLC4420A 数据表(HTML) 6 Page - STMicroelectronics |
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6 / 40 page ![]() Pin descriptions STLC4420A 6/40 2.1 Signal description Table 1. STLC4420A signal descriptions Pin name Pin number Type Internal resistor Function RF front end interface pins LB_LNA_IN- D1 RF input 100 Ω RF Differential Low band (2.4 GHz) 100 Ω RF differential RX inputs. LB_LNA_IN+ C1 RF input HB_LNA_IN- F1 RF input 100 Ω RF Differential High band (5 GHz) 100 Ω RF differential RX inputs. HB_LNA_IN+ E1 RF input LNA_SHIELD C2, C3,D2, E2, F2 RF shield - Low noise amplifier (LNA) input shield pins. LB_TX_OUT H1 RF output - 50 Ω RF transmit (TX) low band (2.4 GHz) single ended output. HB_TX_OUT J1 RF output - 50 Ω RF transmit (TX) low band (5 GHz) single ended output. SW1 A13 digital output - Complementary transmit/receive antennaswitch control outputs. I/O level determined by VDDA supply input. SW2 A14 digital output - SW3 A15 digital output - SW4 A16 digital output - PA_BIAS24 N2, M2 analog output - Power amplifier bias control (2.4 GHz). DAC full-scale output current determined by PA_RREF resistor. PA_BIAS5 L3 analog output - Power amplifier bias control (5 GHz). DAC full-scale output current determined by PA_RREF resistor. PA_RREF N1, M1 analog reference - Analog reference resistor. A 20K ohm typical resistor sets the PA_BIAS full-scale output current. PA_DET0 B12 analog input Resistor ladder PA Detector Input 0. (2.4 GHz) PA_DET1 A12 analog input PA Detector Input 1. (5 GHz) Host interface and clock pins DAT2 F24 1.8 V (VIO) digital I/O SDIO data I/O bit 2. Not used in SPI mode. HOST_IRQ A18 1.8 V digital output, VIO domain Host interrupt request. Typically asserted to request a SPI data transfer. In SDIO mode pin = DAT1. POWER_UP H23 1.8 V digital input 1M Ω Pull-Down Power up enable from host OSC_EN N13 1.8 V digital output No Pull Oscillator enable output. Initially driven high upon powerup, under firmware control after initialization. |
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