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USB7002 数据表(PDF) 29 Page - Microchip Technology

部件名 USB7002
功能描述  4-Port USB 3.2 Gen 1 SmartHub??IC
PDF  56 Pages
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制造商  MICROCHIP [Microchip Technology]
网页  http://www.microchip.com
标志 MICROCHIP - Microchip Technology

USB7002 数据表(HTML) 29 Page - Microchip Technology

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 2022 Microchip Technology Inc. and its subsidiaries
DS00002670G-page 29
USB7002
7.0
DEVICE INTERFACES
The USB7002 provides multiple interfaces for configuration, external memory access, etc.. This section details the var-
ious device interfaces:
• SPI/SQI Master Interface
• SMBus/I2C Master/Slave Interfaces
• I2S Interface
• UART Interface
7.1
SPI/SQI Master Interface
The SPI/SQI controller has two basic modes of operation: execution of an external hub firmware image, or the USB to
SPI bridge. On power up, the firmware looks for an external SPI flash device that contains a valid signature of 2DFU
(device firmware upgrade) beginning at address 0x3FFFA. If a valid signature is found, then the external ROM mode is
enabled and the code execution begins at address 0x0000 in the external SPI device. If a valid signature is not found,
then execution continues from internal ROM and the SPI interface can be used as a USB to SPI bridge.
The second mode of operation is the USB to SPI bridge operation. Additional details on this feature can be found in
Section 8.7, USB to SPI Bridging.
Table 7-1 details how the associated pins are mapped in SPI vs. SQI mode.
7.2
SMBus/I2C Master/Slave Interfaces
The device provides two independent SMBus/I2C controllers (Slave, and Master) which can be used to access internal
device run time registers or program the internal OTP memory. The device contains two 128 byte buffers to enable
simultaneous master/slave operation and to minimize firmware overhead in processed I2C packets. The I2C interfaces
support 100KHz Standard-mode (Sm) and 400KHz Fast Mode (Fm) operation.
The SMBus/I2C interfaces are assigned to programmable pins (PFx) and therefore the device must be programmed into
specific configurations to enable specific interfaces. Refer to Section 3.3.4, PF[31:4] Configuration (CFG_STRAP[2:1])
for additional information.
Note:
For details on how to enable each interface, refer to Section 3.3, Configuration Straps and Programmable
Functions.
For information on device connections, refer to Section 4.0, Device Connections. For information on device
configuration, refer to Section 6.0, Device Configuration.
Microchip provides a comprehensive software programming tool, MPLAB Connect Configurator (formerly
ProTouch2), for configuring the USB7002 functions, registers and OTP memory. All configuration is to be
performed via the MPLAB Connect Configurator programming tool. For additional information on this tool,
refer to th MPLAB Connect Configurator programming tool product page at http://www.microchip.com/
design-centers/usb/mplab-connect-configurator.
TABLE 7-1:
SPI/SQI PIN USAGE
SPI Mode
SQI Mode
Description
SPI_CE_N
SPI_CE_N
SPI/SQI Chip Enable (Active Low)
SPI_CLK
SPI_CLK
SPI/SQI Clock
SPI_D0
SPI_D0
SPI Data Out; SQI Data I/O 0
SPI_D1
SPI_D1
SPI Data In; SQI Data I/O 1
-
SPI_D2
SQI Data I/O 2
-
SPI_D3
SQI Data I/O 3
Note:
For SPI/SQI master timing information, refer to Section 9.6.8, SPI/SQI Master Timing.



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