SML2120 datasheet(4/32 Pages) SUMMIT

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Package and Pin descriptions

SML2120

2066 6.3 1/22/04

Summit Microelectronics

–

PACKAGE AND PIN DESCRIPTIONS

Figure 4. 28-Pin QFN Package Pinout (top view)

PIN DESCRIPTIONS

Pin 1

ENA#

SDA

SCL

AM#

ALERT#

VSS

BIAS

VBURST

MPD

VDD

Pin Number Pin Type

Pin Name

Description

ENA#*

Active low input enables the BIAS, ILU0 and ILU1 output currents.

A1*

The address pins are connected to either the VHI or VLOW pins to provide a

mechanism for assigning a unique I2C bus address to the SML2120.

A2*

4I/O

SDA*

Bi-directional I2C serial data pin

SCL*

I2C serial clock input

AM#*

AM# is an active low input, when asserted the SML2120 is placed in the Auto-

Monitor mode. AM# must be high for programming the Configuration registers

and the Lookup Tables, ILU0 and ILU1 and the general purpose E2PROM.

ALERT#*

Active low, open-drain output indicates when one of the monitored inputs

exceeds its user-programmable high or low alert levels.

8PWR

VLOW

In dual-rail supply voltage systems, VLOW is tied to the system logic low

potential. It is a logic low reference for all pins marked with an asterisk (*).

PWR

VSS

VSS must be tied to the lowest system voltage potential.

PWR

VSS

THERMISTOR

Connect a thermistor to this pin to provide an alternative source of temperature

sensing (see VBRIDGE description).

* See VLOW and VHI pin descriptions.

PACKAGE AND PIN DESCRIPTIONS

PIN DESCRIPTIONS

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