BLP5LA55S

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Product data sheet

Rev. 3 — 16 July 2021

15 of 20

BLP5LA55S

Power LDMOS transistor

8.

Package outline

Fig 18. Package outline SOT1482-1 (sheet 1 of 2)

SOT1482-1

Package outline drawing:

Revision:

Sheet 1 of 2

Revision date:

1/4/2017

Tolerances unless otherwise stated:

Dimension:

0.05

Angle:

1°

Third angle projection

SOT1482-1

6

units in mm.

Exposed Heatsink

Flash/bleed allowed

hatched area (2x)

4.95 (#2)

0.25 A

PIN 1

10.67 0.1 (#4)

0.24

0.025

1.04

7.4 min. 8.7 max.

Compound allowed

0.2

()

#6

#6

#6

1

()

0.5 0.1

9.65 (#1)

A

2.03

0.2 B

B