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NVMJS1D2N04CL 数据表(PDF) 4 Page - ON Semiconductor |
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NVMJS1D2N04CL 数据表(HTML) 4 Page - ON Semiconductor |
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4 / 7 page ![]() NVMJS1D2N04CL www.onsemi.com 4 TYPICAL CHARACTERISTICS Figure 7. Capacitance Variation Figure 8. Gate−to−Source Voltage vs. Total Charge VDS, DRAIN−TO−SOURCE VOLTAGE (V) QG, TOTAL GATE CHARGE (nC) 40 30 20 10 0 10 100 1K 90 70 50 40 20 10 0 0 2 4 6 8 10 Figure 9. Resistive Switching Time Variation vs. Gate Resistance Figure 10. Diode Forward Voltage vs. Current RG, GATE RESISTANCE (W) VSD, SOURCE−TO−DRAIN VOLTAGE (V) 10 1 10 100 0.9 0.8 1.0 0.7 0.6 0.5 0.4 0.3 1 Figure 11. Maximum Rated Forward Biased Safe Operating Area Figure 12. IPEAK vs. Time in Avalanche VDS, DRAIN−TO−SOURCE VOLTAGE (V) TIME IN AVALANCHE (s) 1000 10 1 0.1 0.1 10 100 1000 1 10 VGS = 0 V TJ = 25°C f = 1 MHz CISS COSS CRSS VDS = 32 V ID = 50 A TJ = 25°C QGS QGD VGS = 10 V VDS = 32 V td(off) td(on) tf tr VGS = 0 V TJ = 25°C TJ = −55°C TJ(initial) = 100°C TJ(initial) = 25°C 0.01 RDS(on) Limit Thermal Limit Package Limit 10 ms 0.5 ms 1 ms 10 ms Single Pulse TC = 25°C VGS ≤ 10 V 0.001 1000 35 25 15 5 10K 30 60 TJ = 125°C 10 100 80 100 0.0001 0.00001 100 1 |
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