AnaSem

6

Rev. E13-01

VDD Series

Low voltage, Low power, ±1% High detect accuracy with delay circuit CMOS Voltage Detector

.......... Future of the analog world

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DESCRIPTION OF OPERATION

General operation (CMOS Output)

In reference to following the block diagram of CMOS output VDD series ;

provided at the output terminal because N-ch transistor is OFF and the P-ch transistor is ON. And,

the output maintains the same level of input as long as the input voltage remains above the detection

is ON and the P-ch transistor is OFF. And,

min. operating voltage, the output becomes

level is maintained even though the input

E. Following delay time, the N-ch transistor

the P-Ch transistor becomes ON. And, the

Vss

Voltage

Reference

+

_

P-ch

N-ch

Min. operating voltage

Min. operating voltage

A B

C

D E

[ TIMING CHART ]

Delay

Circuit