AnaSem

2

Rev. E13-01

VDD Series

Low voltage, Low power, ±1% High detect accuracy with delay circuit CMOS Voltage Detector

.......... Future of the analog world

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PRODUCTS NUMBERING GUIDE

PIN CONFIGURATION / MARKING SPECIFICATION (SOT-23)

Pin Configuration

No.

Symbol

Descriptions

1

Output

2

Power ground

3

Voltage input

Marking Specification

Code

Mark

Contents

A

C or N

Output type

BC

18~60

Detection voltage

D

S, M or L

Delay time

E

A

Version

F

Internal rule

Lot number

(Top view)

Vin

Vout

1

2

3

A

F

F F F

B C D E

Vss

VDD

18 ~ 60 : Selectable with a step of 0.1V

in the range of 1.8V ~ 6.0V

e.g.) 18 : 1.8V

30 : 3.0V

Detection voltage

Delay time

S : 10msec~50msec

M : 50msec~200msec

L : 80msec~400msec

Design version

T : SOT-23

Package form

C : CMOS output

N : N-channel open drain output

Output type

Detection accuracy rate

1 : ±1%