USB5744

DS00001855L-page 26

8.2

Resets

The device includes the following chip-level reset sources:

• Power-On Reset (POR)

• External Chip Reset (RESET_N)

• USB Bus Reset

8.2.1

POWER-ON RESET (POR)

A power-on reset occurs whenever power is initially supplied to the device, or if power is removed and reapplied to the

device. A timer within the device will assert the internal reset per the specifications listed in Section 10.6.2, "Power-On

and Configuration Strap Timing," on page 36.

8.2.2

EXTERNAL CHIP RESET (RESET_N)

A valid hardware reset is defined as assertion of RESET_N, after all power supplies are within operating range, per the

specifications in Section 10.6.3, "Reset and Configuration Strap Timing," on page 37. While reset is asserted, the device

(and its associated external circuitry) enters Standby Mode and consumes minimal current.

Assertion of RESET_N causes the following:

1.

The PHY is disabled and the differential pairs will be in a high-impedance state.

2.

All transactions immediately terminate; no states are saved.

3.

All internal registers return to the default state.

4.

The external crystal oscillator is halted.

5.

The PLL is halted.

8.2.3

USB BUS RESET

In response to the upstream port signaling a reset to the device, the device performs the following:

1.

Sets default address to 0.

2.

Sets configuration to Unconfigured.

3.

Moves device from suspended to active (if suspended).

4.

Complies with the USB Specification for behavior after completion of a reset sequence.

The host then configures the device in accordance with the USB Specification.

8.3

Link Power Management (LPM)

The device supports the L0 (On), L1 (Sleep), and L2 (Suspend) link power management states. These supported LPM

states offer low transitional latencies in the tens of microseconds versus the much longer latencies of the traditional USB

suspend/resume in the tens of milliseconds. The supported LPM states are detailed in Table 8-1.

Note:

All power supplies must have reached the operating levels mandated in Section 10.2, "Operating Condi-

tions**," on page 32, prior to (or coincident with) the assertion of RESET_N.

Note:

The device does not propagate the upstream USB reset to downstream devices.

TABLE 8-1:

LPM STATE DEFINITIONS

State

Description

Entry/Exit Time to L0

L2

Suspend

Entry: ~3 ms

Exit: ~2 ms (from start of RESUME)

L1

Sleep

Entry: <10 us

Exit: <50 us

L0

Fully Enabled (On)

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