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SWCS049C 数据表(PDF) 74 Page - Texas Instruments |
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SWCS049C 数据表(HTML) 74 Page - Texas Instruments |
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74 / 144 page  74 TPS65911 SWCS049S – JUNE 2010 – REVISED AUGUST 2018 www.ti.com Submit Documentation Feedback Product Folder Links: TPS65911 Detailed Description Copyright © 2010–2018, Texas Instruments Incorporated Table 6-21. RTC_STATUS_REG Address Offset 0x11 Instance Reset Domain: FULL RESET Description RTC status register: NOTES: A dummy read of this register is necessary before each I2C read in order to update the status register value. Type RW 7 6 5 4 3 2 1 0 POWER_UP ALARM EVENT_1D EVENT_1H EVENT_1M EVENT_1S RUN Reserved Bits Field Name Description Type Reset 7 POWER_UP Indicates that a reset occurred (bit cleared to 0 by writing 1). POWER_UP is set by a reset, is cleared by writing one in this bit. RW 1 6 ALARM Indicates that an alarm interrupt has been generated (bit clear by writing 1). The alarm interrupt keeps its low level, until the microcontroller write 1 in the ALARM bit of the RTC_STATUS_REG register. The timer interrupt is a low-level pulse (15 µs duration). RW 0 5 EVENT_1D One day has occurred RO 0 4 EVENT_1H One hour has occurred RO 0 3 EVENT_1M One minute has occurred RO 0 2 EVENT_1S One second has occurred RO 0 1 RUN 0: RTC is frozen 1: RTC is running This bit shows the real state of the RTC, indeed because of STOP_RTC signal was resynchronized on 32-kHz clock, the action of this bit is delayed. RO 0 0 Reserved Reserved bit RO R returns 0s 0 |
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