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SWCS049D 数据表(PDF) 75 Page - Texas Instruments |
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SWCS049D 数据表(HTML) 75 Page - Texas Instruments |
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75 / 144 page  75 TPS65911 www.ti.com SWCS049S – JUNE 2010 – REVISED AUGUST 2018 Submit Documentation Feedback Product Folder Links: TPS65911 Detailed Description Copyright © 2010–2018, Texas Instruments Incorporated Table 6-22. RTC_INTERRUPTS_REG Address Offset 0x12 Instance Reset Domain: FULL RESET Description RTC interrupt control register Type RW 7 6 5 4 3 2 1 0 Reserved IT_SLEEP_ MASK_EN IT_ALARM IT_TIMER EVERY Bits Field Name Description Type Reset 7:5 Reserved Reserved bit RO R returns 0s 0x0 4 IT_SLEEP_MASK_E N 1: Mask periodic interrupt while the TPS65911 device is in SLEEP mode. Interrupt event is back up in a register and occurred as soon as the TPS65911 device is no more in SLEEP mode. 0: Normal mode, no interrupt masked RW 0 3 IT_ALARM Enable one interrupt when the alarm value is reached (TC ALARM registers) by the TC registers RW 0 2 IT_TIMER Enable periodic interrupt 0: interrupt disabled 1: interrupt enabled RW 0 1:0 EVERY Interrupt period 00: each second 01: each minute 10: each hour 11: each day RW 0x0 Table 6-23. RTC_COMP_LSB_REG Address Offset 0x13 Instance Reset Domain: FULL RESET Description RTC compensation register (LSB) Notes: This register must be written in 2-complement. This means that to add one 32-kHz oscillator period each hour, microcontroller needs to write FFFF into RTC_COMP_MSB_REG and RTC_COMP_LSB_REG. To remove one 32-kHz oscillator period each hour, microcontroller needs to write 0001 into RTC_COMP_MSB_REG and RTC_COMP_LSB_REG. The 7FFF value is forbidden. Type RW 7 6 5 4 3 2 1 0 RTC_COMP_LSB Bits Field Name Description Type Reset 7:0 RTC_COMP_LSB This register contains the number of 32-kHz periods to be added into the 32-kHz counter each hour [LSB] RW 0x00 |
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