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CC400-RTR2 数据表(PDF) 12 Page - Texas Instruments |
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CC400-RTR2 数据表(HTML) 12 Page - Texas Instruments |
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12 / 31 page  CC400 SWRS050 Page 12 of 32 Parameter Symbol Min Max Units Conditions CLOCK, clock frequency FCLOCK - 2 MHz CLOCK low pulse duration TCL,min 50 ns The minimum time CLOCK can be low. CLOCK high pulse duration TCH,min 50 ns The minimum time CLOCK can be high. PDATA setup time TSD 5 - ns The minimum time data on PDATA must be ready before the negative edge of CLOCK. PDATA hold time THD 5 - ns The minimum time data must be held at PDATA, after the negative edge of CLOCK. CLOCK to STROBE time TCS 5 - ns The minimum time after the negative edge of CLOCK before positive edge of STROBE. STROBE to CLOCK time TSC 5 - ns The minimum time after the negative edge of STROBE before negative edge of CLOCK. STROBE pulse duration TS,min 50 ns The minimum time STROBE can be high. Rise time Trise 100 ns The maximum rise time for CLOCK and STROBE Fall time Tfall 100 ns The maximum fall time for CLOCK and STROBE Note: The set-up- and hold-times refer to 50% of VDD. Table 10: Serial interface, timing specification. |
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