DPD Demodulator for PA

Linearization, 1300MHz to 2900MHz

IDTF1350

Datasheet

6

January 21, 2020

The power-on sequence ensures F1350 works in default mode once powered on. If the F1350 is programmed after

applying DC power, the following power-on sequence is not needed. Note: To use power on sequence, SW_LATCH

cannot be grounded permanently.

The power-on sequence should be:

1. CSb & SW_LATCH must be set low at power-on

2. Once powered on, first set SW_LATCH high, then set CSb high

3. Proceed with normal programming.

The default state after using power-on sequence:

•

Maximum attenuation

•

RF_INX selected

•

Normal operation (not Standby Mode)

The device is programmed via the serial port by asserting Chip Select (CSb). Note: Most-Significant-Bit first,

where the Address Word is the Most-Significant-Byte.

Serial mode timing diagram high level:

Address Word A7 – A0

Data Word D7 – D0

D5 D4

D0

D3

D1

D2

16 dB

RFSW

CLK

DATA

Data Word

Latched into

Register

LSB

CS

RSV

RSV

RSV

RSV

RSV

RSV

RSV

0

0

ENb

0

0

0

0

0

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

8 dB 4 dB

2 dB 1 dB 0.5 dB

MSB

1 = RFY

0 = RFX

1 = OFF

0 = ON

Polarity:

1 = ATTN ON

0 = ATTN OFF

SW_Latch

Clock in MSB first

Increasing time

RSV

0

D6

D7

A5 A4

A0

A3

A1

A2

A6

A7