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by 8 of the internal reference clock for DDR transfers. Tap mode only supports one clocking topology for the

receive data capture clock. No Loopback - uses the internal reference clock as the Tap receive data capture

clock. This clocking topology supports a maximum internal reference clock rate of 200 MHz, which produces an

OSPI0_CLK rate up to 50 MHz for SDR mode or 25 MHz for DDR mode.

For more information, see Octal Serial Peripheral Interface (OSPI) section in Peripherals chapter in the device

TRM.

For more details about features and additional description information on the device Octal Serial Peripheral

Interface, see the corresponding subsections within Signal Descriptions and Detailed Description sections.

Section 7.10.5.14.1 defines timing requirements and switching characteristics associated with PHY mode and

Section 7.10.5.14.2 defines timing requirements and switching characteristics associated with Tap mode.

Table 7-93 presents timing conditions for OSPI0.

Table 7-93. OSPI0 Timing Conditions

PARAMETER

MODE

MIN

MAX UNIT

INPUT CONDITIONS

SRI

Input slew rate

V/ns

OUTPUT CONDITIONS

Output load capacitance

PCB CONNECTIVITY REQUIREMENTS

td(Trace Delay)

Propagation delay of OSPI0_CLK trace

No Loopback

Internal PHY Loopback

Internal Pad Loopback

450

Propagation delay of OSPI0_LBCLKO

trace

External Board Loopback

2L(1) - 30

2L(1) + 30

Propagation delay of OSPI0_DQS trace

DQS

L(1) - 30

L(1) + 30

td(Trace Mismatch

Delay)

Propagation delay mismatch of

OSPI0_D[7:0] and OSPI0_CSn[3:0]

relative to OSPI0_CLK

All modes

(1)

L = Propagation delay of OSPI0_CLK trace

7.10.5.14.1 OSPI0 PHY Mode

7.10.5.14.1.1 OSPI0 With PHY Data Training

Read and write data valid windows will shift due to variation in process, voltage, temperature, and operating

frequency. A data training method may be implemented to dynamically configure optimal read and write timing.

Implementing data training enables proper operation across temperature with a specific process, voltage, and

frequency operating condition, while achieving a higher operating frequency.

Data transmit and receive timing parameters are not defined for the data training use case since they are

dynamically adjusted based on the operating condition.

Table 7-94 defines DLL delays required for OSPI0 with Data Training. Table 7-95, Figure 7-80 Table 7-96, and

Figure 7-81 present timing requirements and switching characteristics for OSPI0 with Data Training.

Table 7-94. OSPI0 DLL Delay Mapping for PHY Data Training

MODE

OSPI_PHY_CONFIGURATION_REG BIT FIELD

DELAY VALUE

Transmit

All modes

PHY_CONFIG_TX_DLL_DELAY_FLD,

(1)

Receive

All modes

PHY_CONFIG_RX_DLL_DELAY_FLD

(2)

(1)

Transmit DLL delay value determined by training software

(2)

Receive DLL delay value determined by training software

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AM6442, AM6441, AM6421, AM6412, AM6411

SPRSP56D – JANUARY 2021 – REVISED JULY 2022

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