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Table 7-95. OSPI0 Timing Requirements – PHY Data Training

see Figure 7-80

NO.

MODE

MIN

MAX

UNIT

O15

tsu(D-LBCLK)

Setup time, OSPI0_D[7:0] valid before

active OSPI0_DQS edge

DDR with DQS

(1)

O16

th(LBCLK-D)

Hold time, OSPI0_D[7:0] valid after active

OSPI0_DQS edge

DDR with DQS

(1)

Minimum setup and hold time requirements for OSPI0_D[7:0] inputs are not defined when Data Training is used to find the optimum

data valid window.

OSPI_DQS

O16

O15

OSPI_TIMING_04

OSPI_D[i:0]

O16

O15

Figure 7-80. OSPI0 Timing Requirements – PHY Data Training, DDR with DQS

Table 7-96. OSPI Switching Characteristics – PHY Data Training

See Figure 7-81

NO.

PARAMETER

MODE

MIN

MAX

UNIT

tc(CLK)

Cycle time, OSPI0_CLK

1.8V, DDR

6.02

3.3V, DDR

7.52

tw(CLKL)

Pulse duration, OSPI0_CLK low

DDR

((0.475P(1)) - 0.3)

tw(CLKH)

Pulse duration, OSPI0_CLK high

DDR

((0.475P(1)) - 0.3)

td(CLK-CSn)

Delay time, OSPI0_CSn[3:0] active edge

to OSPI0_CLK rising edge

DDR

TBD

td(CLK-CSn)

Delay time, OSPI0_CLK rising edge to

OSPI0_CSn[3:0] inactive edge

DDR

TBD

td(CLK-D)

Delay time, OSPI0_CLK active edge to

OSPI0_D[7:0] transition

DDR

(2)

(1)

P = OSPI0_CLK cycle time = SCLK period in ns

(2)

Minimum and maximum delay times for OSPI0_D[7:0] outputs are not defined when Data Training is used to find the optimum data

valid window.

OSPI_CLK

OSPI_TIMING_01

OSPI_CSn

OSPI_D[i:0]

Figure 7-81. OSPI0 Switching Characteristics – PHY DDR Data Training

AM6442, AM6441, AM6421, AM6412, AM6411

SPRSP56D – JANUARY 2021 – REVISED JULY 2022

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