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OSPI_CLK

OSPI_TIMING_01

OSPI_CSn

OSPI_D[i:0]

Figure 7-86. OSPI0 Switching Characteristics – PHY DDR

7.10.5.14.2 OSPI0 Tap Mode

7.10.5.14.2.1 OSPI0 Tap SDR Timing

Table 7-103, Figure 7-87, Table 7-104, and Figure 7-88 present timing requirements and switching

characteristics for OSPI0 Tap SDR Mode.

Table 7-103. OSPI0 Timing Requirements – Tap SDR Mode

see Figure 7-87

NO.

MODE

MIN

MAX

UNIT

O19

tsu(D-CLK)

Setup time, OSPI0_D[7:0] valid before

active OSPI0_CLK edge

No Loopback

(10.4 -

(0.975T(1)R(2)))

O20

th(CLK-D)

Hold time, OSPI0_D[7:0] valid after active

OSPI0_CLK edge

No Loopback

(0.7 +

(0.975T(1)R(2)))

(1)

T = OSPI_RD_DATA_CAPTURE_REG[DELAY_FLD]

(2)

R = refclk cycle time in ns

OSPI_CLK

OSPI_D[i:0]

OSPI_TIMING_05

O 9

O20

Figure 7-87. OSPI0 Timing Requirements – Tap SDR, No Loopback

Table 7-104. OSPI0 Switching Characteristics – Tap SDR Mode

see Figure 7-88

NO.

PARAMETER

MODE

MIN

MAX

UNIT

tc(CLK)

Cycle time, OSPI0_CLK

tw(CLKL)

Pulse duration, OSPI0_CLK low

((0.475P(1)) - 0.3)

tw(CLKH)

Pulse duration, OSPI0_CLK high

((0.475P(1)) - 0.3)

O10

td(CLK-CSn)

Delay time, OSPI0_CSn[3:0] active edge

to OSPI0_CLK rising edge

((0.475P(1)) +

(0.975M(2)R(4)) - 1)

((0.525P(1)) +

(1.025M(2)R(4)) + 1)

O11

td(CLK-CSn)

Delay time, OSPI0_CLK rising edge to

OSPI0_CSn[3:0] inactive edge

((0.475P(1)) +

(0.975N(3)R(4)) - 1)

((0.525P(1)) +

(1.025N(3)R(4)) + 1)

O12

td(CLK-D)

Delay time, OSPI0_CLK active edge to

OSPI0_D[7:0] transition

- 4.25

7.25

(1)

P = CLK cycle time = SCLK period in ns

AM6442, AM6441, AM6421, AM6412, AM6411

SPRSP56D – JANUARY 2021 – REVISED JULY 2022

www.ti.com

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