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AM6422...ALV 数据表(PDF) 200 Page - Texas Instruments |
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AM6422...ALV 数据表(HTML) 200 Page - Texas Instruments |
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200 / 244 page  7.10.5.16.3 PRU_ICSSG Industrial Ethernet Peripheral (IEP) Table 7-118. PRU_ICSSG IEP Timing Conditions PARAMETER MIN MAX UNIT INPUT CONDITIONS SRI Input slew rate 1 3 V/ns OUTPUT CONDITIONS CL Output load capacitance EDC_SYNC_OUTx EDIO_OUTVALID 2 7 pF EDIO_DATA_OUT 3 10 pF 7.10.5.16.3.1 PRU_ICSSG IEP Timing Table 7-119. PRU_ICSSG IEP Timing Requirements – Input Validated with SYNC see Figure 7-101 NO. PARAMETER DESCRIPTION MIN MAX UNIT PRIEP1 tw(EDC_SYNC_OUTxL) Pulse duration, EDC_SYNC_OUTx low 20P(1) - 2 ns PRIEP2 tw(EDC_SYNC_OUTxH) Pulse duration, EDC_SYNC_OUTx high 20P(1) - 2 ns PRIEP3 tsu(EDIO_DATA_IN- EDC_SYNC_OUTx) Setup time, EDIO_DATA_IN valid before EDC_SYNC_OUTx active edge 20 ns PRIEP4 th(EDC_SYNC_OUTx- EDIO_DATA_IN) Hold time, EDIO_DATA_IN valid after EDC_SYNC_OUTx active edge 20 ns (1) P = PRU_ICSSG IEP clock source period in ns. EDC_SYNC_OUTx PRIEP4 PRIEP2 PRIEP3 EDIO_DATA_IN[7:0] PRU_IEP_TIMING_01 PRIEP1 Figure 7-101. PRU_ICSSG IEP SYNC Timing Requirements Table 7-120. PRU_ICSSG IEP Switching Characteristics – Digital IOs see Figure 7-102 NO. PARAMETER DESCRIPTION MIN MAX UNIT IEPIO1 tw(EDIO_OUTVALIDL) Pulse duration, EDIO_OUTVALID low 14P(1) - 2 ns IEPIO2 tw(EDIO_OUTVALIDH) Pulse duration, EDIO_OUTVALID high 32P(1) - 2 ns IEPIO3 td(EDIO_OUTVALID- EDIO_DATA_OUT) Delay time, EDIO_OUTVALID to EDIO_DATA_OUT 0 18P(1) ns IEPIO4 tsk(EDIO_DATA_OUT) EDIO_DATA_OUT skew 5 ns (1) P = PRU_ICSSG IEP clock source period in ns. AM6442, AM6441, AM6421, AM6412, AM6411 SPRSP56D – JANUARY 2021 – REVISED JULY 2022 www.ti.com 200 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: AM6442 AM6441 AM6421 AM6412 AM6411 |
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