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AM6422...ALV 数据表(PDF) 203 Page - Texas Instruments |
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AM6422...ALV 数据表(HTML) 203 Page - Texas Instruments |
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203 / 244 page  APWM PREP3 SYNCO PREP4 Figure 7-106. PRU_ICSSG ECAP Switching Characteristics 7.10.5.16.6 PRU_ICSSG RGMII, MII_RT, and Switch For more information, see Programmable Real-Time Unit Subsystem and Industrial Communication Subsystem - Gigabit (PRU_ICSSG) section in Processors and Accelerators chapter in the device TRM. 7.10.5.16.6.1 PRU_ICSSG MDIO Timing Table 7-128, Table 7-129, Table 7-130, and Figure 7-107 present timing conditions, requirements, and switching characteristics for PRU_ICSSG MDIO. Table 7-128. PRU_ICSSG MDIO Timing Conditions PARAMETER MIN MAX UNIT INPUT CONDITIONS SRI Input slew rate 0.9 3.6 V/ns OUTPUT CONDITIONS CL Output load capacitance 10 470 pF Table 7-129. PRU_ICSSG MDIO Timing Requirements see Figure 7-107 NO. PARAMETER MIN MAX UNIT MDIO1 tsu(MDIO_MDC) Setup time, MDIO[x]_MDIO valid before MDIO[x]_MDC high 90 ns MDIO2 th(MDC_MDIO) Hold time, MDIO[x]_MDIO valid after MDIO[x]_MDC high 0 ns Table 7-130. PRU_ICSSG MDIO Switching Characteristics see Figure 7-107 NO. PARAMETER MIN MAX UNIT MDIO3 tc(MDC) Cycle time, MDIO[x]_MDC 400 ns MDIO4 tw(MDCH) Pulse Duration, MDIO[x]_MDC high 160 ns MDIO5 tw(MDCL) Pulse Duration, MDIO[x]_MDC low 160 ns MDIO7 td(MDC_MDIO) Delay time, MDIO[x]_MDC low to MDIO[x]_MDIO valid -150 150 ns www.ti.com AM6442, AM6441, AM6421, AM6412, AM6411 SPRSP56D – JANUARY 2021 – REVISED JULY 2022 Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 203 Product Folder Links: AM6442 AM6441 AM6421 AM6412 AM6411 |
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