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AM6422...ALV 数据表(PDF) 206 Page - Texas Instruments |
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AM6422...ALV 数据表(HTML) 206 Page - Texas Instruments |
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206 / 244 page  MII_TX_CLK PMIT2 PMIT3 PMIT1 Figure 7-110. PRU_ICSSG MII[x]_TX_CLK Timing Table 7-135. PRU_ICSSG MII Switching Characteristics – MII[x]_TXD[3:0] and MII[x]_TX_EN see Figure 7-111 NO. PARAMETER DESCRIPTION MODE MIN MAX UNIT PMIT4 td(TX_CLK-TXD) Delay time, MII[x]_TX_CLK High to MII[x]_TXD[3:0] valid 10 Mbps 0 25 ns td(TX_CLK-TX_EN) Delay time, MII[x]_TX_CLK to MII[x]_TX_EN valid 0 25 ns td(TX_CLK-TXD) Delay time, MII[x]_TX_CLK High to MII[x]_TXD[3:0] valid 100 Mbps 0 25 ns td(TX_CLK-TX_EN) Delay time, MII[x]_TX_CLK to MII[x]_TX_EN valid 0 25 ns PMIT4 MII_TX_CLK MII_TXD[3:0], MII_TX_EN Figure 7-111. PRU_ICSSG MII[x]_TXD[3:0], MII[x]_TX_EN Timing 7.10.5.16.6.3 PRU_ICSSG RGMII Timing Table 7-136, Table 7-137, Table 7-138, Figure 7-112, Table 7-139, Table 7-140, and Figure 7-113 present timing conditions, requirements, and switching characteristics for PRU_ICSSG RGMII. Table 7-136. PRU_ICSSG RGMII Timing Conditions PARAMETER MIN MAX UNIT INPUT CONDITIONS SRI Input slew rate VDD = 1.8V 1.44 5 V/ns VDD = 3.3V 2.65 5 V/ns OUTPUT CONDITIONS CL Output load capacitance 2 20 pF PCB CONNECTIVITY REQUIREMENTS td(Trace Mismatch Delay) Propagation delay mismatch across all traces RGMII[x]_RXC, RGMII[x]_RD[3:0], RGMII[x]_RX_CTL 50 ps RGMII[x]_TXC, RGMII[x]_TD[3:0], RGMII[x]_TX_CTL 50 ps Table 7-137. PRU_ICSSG RGMII Timing Requirements – RGMII[x]_RXC see Figure 7-112 NO. PARAMETER DESCRIPTION MODE MIN MAX UNIT RGMII1 tc(RXC) Cycle time, RGMII[x]_RXC 10 Mbps 360 440 ns 100 Mbps 36 44 ns 1000 Mbps 7.2 8.8 ns RGMII2 tw(RXCH) Pulse duration, RGMII[x]_RXC high 10 Mbps 160 240 ns 100 Mbps 16 24 ns 1000 Mbps 3.6 4.4 ns AM6442, AM6441, AM6421, AM6412, AM6411 SPRSP56D – JANUARY 2021 – REVISED JULY 2022 www.ti.com 206 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: AM6442 AM6441 AM6421 AM6412 AM6411 |
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