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8.3 Accelerators and Coprocessors

8.3.1 Programmable Real-Time Unit Subsystem and Industrial Communication Subsystem (PRU_ICSSG)

The PRU_ICSSG module supports the following main features:

• 3x PRUs

– General-Purpose PRU (PRU)

– Real-Time PRU(RTU_PRU)

– Transmit PRU (TX_PRU)

• 2x Ethernet MII_G_RT configurable connection to PRUs

– Up to 2x RGMII ports

– Up to 2x MII ports

– RX Classifier

• 2x Industrial Ethernet Peripheral (IEP) to manage and generate industrial Ethernet functions

• 2x Industrial Ethernet 64-bit timers, each with 10 capture and 16 compare events, along with slow and fast

compensation.

• 1x MDIO

• 1x UART, with a dedicated 192-MHz clock input

• Supports up to 4 sets of 3-phased motor control, with 12 primary and 12 complimentary programmable PWM

outputs.

• Supports up to 9 safety events with optional external trip I/O per PWM set with hardware glitch filter.

• 1x Enhanced Capture Module (ECAP)

• 1x Interrupt Controller (INTC)

– 160 input events supported – 96 external, 64 internal

• Flexible power management support

• Integrated switched central resource with programmable priority

• All memories support ECC

For more information, see Programmable Real-Time Unit Subsystem and Industrial Communication Subsystem -

Gigabit (PRU_ICSSG) section in Processors and Accelerators chapter in the device TRM.

8.4 Other Subsystems

8.4.1 PDMA Controller

The Peripheral DMA is a simple DMA which has been architected to specifically meet the data transfer

needs of peripherals, which perform data transfers using memory mapped registers accessed via a standard

non-coherent bus fabric. The PDMA module is intended to be located close to one or more peripherals which

require an external DMA for data movement and is architected to reduce cost by using VBUSP interfaces and

supporting only statically configured Transfer Request (TR) operations.

The PDMA is only responsible for performing the data movement transactions which interact with the peripherals

themselves. Data which is read from a given peripheral is packed by a PDMA source channel into a PSI-L data

stream which is then sent to a remote peer UDMA-P destination channel which then performs the movement of

the data into memory. Likewise, a remote UDMA-P source channel fetches data from memory and transfers it to

a peer PDMA destination channel over PSI-L which then performs the writes to the peripheral.

The PDMA architecture is intentionally heterogeneous (UDMA-P + PDMA) to right size the data transfer

complexity at each point in the system to match the requirements of whatever is being transferred to or

from. Peripherals are typically FIFO based and do not require multi-dimensional transfers beyond their FIFO

dimensioning requirements, so the PDMA transfer engines are kept simple with only a few dimensions (typically

for sample size and FIFO depth), hardcoded address maps, and simple triggering capabilities.

Multiple source and destination channels are provided within the PDMA which allow multiple simultaneous

transfer operations to be ongoing. The DMA controller maintains state information for each of the channels and

employs round-robin scheduling between channels in order to share the underlying DMA hardware.

There are five PDMA modules in the device.

For more information, see PDMA Controller section in DMA Controllers chapter in the device TRM.

AM6442, AM6441, AM6421, AM6412, AM6411

SPRSP56D – JANUARY 2021 – REVISED JULY 2022

www.ti.com

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