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8.4.2 Peripherals

8.4.2.1 ADC

The analog-to-digital converter (ADC) module is an single-channel general purpose analog-to-digital converter

with a 8-input analog multiplexer, which supports 12-bit conversion samples from an analog front end (AFE).

There is one ADC module in the device.

For more information, see Analog-to-Digital Converter (ADC) section in Peripherals chapter in the device TRM.

8.4.2.2 DCC

The Dual Clock Comparator (DCC) is used to determine the accuracy of a clock signal during the time

execution of an application. Specifically, the DCC is designed to detect drifts from the expected clock frequency.

The desired accuracy can be programed based on calculation for each application. The DCC measures the

frequency of a selectable clock source using another input clock as a reference.

The device has seven instances of DCC modules.

For more information, see Dual Clock Comparator (DCC) section in Peripherals chapter in the device TRM.

8.4.2.3 Dual Date Rate (DDR) External Memory Interface (DDRSS)

Integrated in MAIN domain: one instance of DDR Subsystem (DDRSS) is used as an interface to external RAM

devices which can be utilized for storing program or data. DDRSS provides the following main features:

• Support of DDR4 / LPDDR4 memory types

• 16-bit memory bus interface with in-line ECC

• System bus interface: little endian only with 128-bit data width

• Configuration bus Interface: little endian only with 32-bit data width

• Support of dual rank configuration

• Support of automatic idle power saving mode when no or low activity is detected

• Class of Service (CoS) - three latency classes supported

• Prioritized refresh scheduling

• Statistical counters for performance management

For more information, see DDR Subsystem (DDRSS) section in Peripherals chapter in the device TRM.

8.4.2.4 ECAP

This section describes the Enhanced Capture (ECAP) module for the device.

For more information, see Enhanced Capture (ECAP) Module section in Peripherals chapter in the device TRM.

8.4.2.5 EPWM

An effective PWM peripheral must be able to generate complex pulse width waveforms with minimal CPU

overhead or intervention. It needs to be highly programmable and very flexible while being easy to understand

and use. The EPWM unit described here addresses these requirements by allocating all needed timing and

control resources on a per PWM channel basis. Cross coupling or sharing of resources has been avoided;

instead, the EPWM is built up from smaller single channel modules with separate resources and that can

operate together as required to form a system. This modular approach results in an orthogonal architecture and

provides a more transparent view of the peripheral structure, helping users to understand its operation quickly.

In the further description the letter x within a signal or module name is used to indicate a generic EPWM instance

on a device. For example, output signals EPWMxA and EPWMxB refer to the output signals from the EPWM_x

instance. Thus, EPWM1A and EPWM1B belong to EPWM1, EPWM2A and EPWM2B belong to EPWM2, and so

forth.

Additionally, the EPWM integration allows this synchronization scheme to be extended to the capture peripheral

modules (ECAP). The number of modules is device-dependent and based on target application needs. Modules

can also operate stand-alone.

The device has six instances of EPWM modules.

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AM6442, AM6441, AM6421, AM6412, AM6411

SPRSP56D – JANUARY 2021 – REVISED JULY 2022

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