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AM6421...ALV 数据表(PDF) 41 Page - Texas Instruments

部件名 AM6421...ALV
功能描述  AM64x Sitara™ Processors
PDF  244 Pages
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制造商  TI [Texas Instruments]
网页  http://www.ti.com
标志 TI - Texas Instruments

AM6421...ALV 数据表(HTML) 41 Page - Texas Instruments

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Table 6-1. Pin Attributes (ALV Package) (continued)
BALL
NUMBER [1]
BALL NAME [2]
PADCONFIG Register [15]
PADCONFIG Address [16]
SIGNAL NAME [3]
MUX
MODE
[4]
TYPE
[5]
DSIS
[6]
BALL
STATE
DURING
RESET
RX/TX/PULL [7]
BALL
STATE
AFTER
RESET
RX/TX/PULL [8]
MUX
MODE
AFTER
RESET
[9]
I/O
OPERATING
VOLTAGE [10]
POWER [11]
HYS
[12]
BUFFER
TYPE [13]
PULL
UP/DOWN
TYPE [14]
Y5
PRG0_PRU1_GPO9
PADCONFIG:
PADCONFIG117
0x000F41D4
PRG0_PRU1_GPO9
0
IO
0
Off / Off / Off
Off / Off / Off
7
1.8 V/3.3 V
VDDSHV1
Yes
LVCMOS
PU/PD
PRG0_PRU1_GPI9
1
I
0
PRG0_UART0_RXD
2
I
1
RGMII1_RD1
4
I
0
RMII1_RXD1
5
I
0
PRG0_IEP0_EDIO_DATA_IN_OUT30
6
IO
0
GPIO1_29
7
IO
pad
EQEP0_I
8
IO
0
UART5_RXD
10
I
1
V6
PRG0_PRU1_GPO10
PADCONFIG:
PADCONFIG118
0x000F41D8
PRG0_PRU1_GPO10
0
IO
0
Off / Off / Off
Off / Off / Off
7
1.8 V/3.3 V
VDDSHV1
Yes
LVCMOS
PU/PD
PRG0_PRU1_GPI10
1
I
0
PRG0_UART0_TXD
2
O
PRG0_PWM2_TZ_IN
3
I
0
RGMII1_RD2
4
I
0
RMII1_TXD0
5
O
PRG0_IEP0_EDIO_DATA_IN_OUT31
6
IO
0
GPIO1_30
7
IO
pad
EQEP1_I
8
IO
0
UART6_RXD
10
I
1
W4
PRG0_PRU1_GPO11
PADCONFIG:
PADCONFIG119
0x000F41DC
PRG0_PRU1_GPO11
0
IO
0
Off / Off / Off
Off / Off / Off
7
1.8 V/3.3 V
VDDSHV1
Yes
LVCMOS
PU/PD
PRG0_PRU1_GPI11
1
I
0
PRG0_RGMII2_TD0
2
O
GPIO1_31
7
IO
pad
EQEP2_I
8
IO
0
UART4_RXD
10
I
1
Y4
PRG0_PRU1_GPO12
PADCONFIG:
PADCONFIG120
0x000F41E0
PRG0_PRU1_GPO12
0
IO
0
Off / Off / Off
Off / Off / Off
7
1.8 V/3.3 V
VDDSHV1
Yes
LVCMOS
PU/PD
PRG0_PRU1_GPI12
1
I
0
PRG0_RGMII2_TD1
2
O
PRG0_PWM1_A0
3
IO
0
GPIO1_32
7
IO
pad
EQEP2_B
8
I
0
GPMC0_A7
9
OZ
UART4_TXD
10
O
www.ti.com
AM6442, AM6441, AM6421, AM6412, AM6411
SPRSP56D – JANUARY 2021 – REVISED JULY 2022
Copyright © 2022 Texas Instruments Incorporated
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Product Folder Links: AM6442 AM6441 AM6421 AM6412 AM6411



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