AM6421...ALV datasheet(114/244 Pages) TI

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7.10.2.2.1 Power-Up Sequencing

Figure 7-5 describes the device power-up sequencing.

AM64x_ELCH_01

VDDSHV_MCU , VDDSHV0 , VDDSHV1 , VDDSHV2 , VDDSHV3 ,

(3)

VDDSHV4 , VDDSHV5 , VDDA_3P3_SDIO, VDDA_3P3_USB0,

(3)

VMON_3P3_SOC , VMON_3P3_MCU

(4)

VSYS, VMON_VSYS

VDDS_OSC, VDDSHV_MCU , VDDSHV0 , VDDSHV1 , VDDSHV2 , VDDSHV3 ,

(5)

VDDSHV4 , VDDSHV5 , VDDA_MCU, VDDA_ADC0, VDDA_PLL0, VDDA_PLL1,

(5)

VDDA_PLL2, VDDA_1P8_SERDES0, VDDA_1P8_USB0, VMON_1P8_MCU ,

(6)

VMON_1P8_SOC , VDDA_TEMP0, VDDA_TEMP1, VDDS_MMC0

(6)

VDDS_DDR , VDDS_DDR_C

(7)

VDD_CORE

(8)(10)

VDD_CORE

, VDDR_CORE

, VDDA_0P85_SERDES0_C,

(9)(10)

(10)

VDDA_0P85_SERDES0, VDDA_0P85_USB0,

VDD_DLL_MMC0, VDD_MMC0

VPP

(11)

MCU_PORz

MCU_OSC0_XI, MCU_OSC0_XO

Hi-Z

VSYS

VMON_VSYS

Note 1

Note 2

Figure 7-5. Power-Up Sequencing

1. VSYS represents the name of a supply which sources power to the entire system. This supply is expected to

be a pre-regulated supply that sources power management devices which source all other supplies.

2. VMON_VSYS input is used to monitor VSYS via an external resistor divider circuit. For more information,

see Section 9.3.4, System Power Supply Monitor Design Guidelines.

3. VDDSHV_MCU and VDDSHVx [x=0-5] are dual voltage IO supplies which can be operated at 1.8V or

3.3V depending on the application requirements. When any of the VDDSHV_MCU or VDDSHVx [x=0-5] IO

supplies are operating at 3.3V, they shall be ramped up with other 3.3V supplies during the 3.3V ramp period

defined by this waveform.

4. The VMON_3P3_MCU and VMON_3P3_SOC inputs are used to monitor supply voltage and shall be

connected to the respective 3.3V supply source.

5. VDDSHV_MCU and VDDSHVx [x=0-5] are dual voltage IO supplies which can be operated at 1.8V or

3.3V depending on the application requirements. When any of the VDDSHV_MCU or VDDSHVx [x=0-5] IO

supplies are operating at 1.8V, they shall be ramped up with other 1.8V supplies during the 1.8V ramp period

defined by this waveform.

6. The VMON_1P8_MCU and VMON_1P8_SOC inputs are used to monitor supply voltage and shall be

connected to the respective 1.8V supply source.

7. VDDS_DDR and VDDS_DDR_C are expected to be powered by the same source such that they ramp

together.

8. VDD_CORE can be operated at 0.75V or 0.85V. When VDD_CORE is operating at 0.75V, it shall be ramped

up prior to all 0.85V supplies as shown in this waveform.

9. VDD_CORE can be operated at 0.75V or 0.85V. When VDD_CORE is operating at 0.85V, it shall be ramped

up with other 0.85V supplies during the 0.85V ramp period defined by this waveform.

AM6442, AM6441, AM6421, AM6412, AM6411

SPRSP56D – JANUARY 2021 – REVISED JULY 2022

www.ti.com

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