AM6421...ALV datasheet(145/244 Pages) TI

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Table 7-53. GPMC and NOR Flash Switching Characteristics – Synchronous Mode (continued)

see Figure 7-39, Figure 7-40, Figure 7-41, Figure 7-42, and Figure 7-43

NO.

(3)

PARAMETER

DESCRIPTION

MODE

(17)

MIN

MAX

MIN

MAX

UNIT

100 MHz

133 MHz

tw(clkL)

Typical pulse duration, output clock

GPMC_CLK low

div_by_1_mode;

GPMC_FCLK_MUX;

TIMEPARAGRANULARITY_X1

0.475P

- 0.3(15)

0.475P

- 0.3(15)

td(clkH-csnV)

Delay time, output clock GPMC_CLK

rising edge to output chip select

GPMC_CSn[i] transition

(14)

div_by_1_mode;

GPMC_FCLK_MUX;

TIMEPARAGRANULARITY_X1;

no extra_delay

F - 2.2

(6)

F +

3.75

F - 2.2

(6)

F +

3.75

td(clkH-CSn[i]V)

Delay time, output clock GPMC_CLK

rising edge to output chip select

GPMC_CSn[i] invalid

(14)

div_by_1_mode;

GPMC_FCLK_MUX;

TIMEPARAGRANULARITY_X1;

no extra_delay

E - 2.2

(5)

E +

3.18

E - 2.2

(5)

E + 4.5

td(aV-clk)

Delay time, output address

GPMC_A[27:1] valid to output clock

GPMC_CLK first edge

div_by_1_mode;

GPMC_FCLK_MUX;

TIMEPARAGRANULARITY_X1

B - 2.3

(3)

B + 4.5 B - 2.3

(3)

B + 4.5

td(clkH-aIV)

Delay time, output clock GPMC_CLK

rising edge to output address

GPMC_A[27:1] invalid

div_by_1_mode;

GPMC_FCLK_MUX;

TIMEPARAGRANULARITY_X1

-2.3

4.5

-2.3

4.5

td(be[x]nV-clk)

Delay time, output lower byte

enable and command latch enable

GPMC_BE0n_CLE, output upper byte

enable GPMC_BE1n valid to output

clock GPMC_CLK first edge

div_by_1_mode;

GPMC_FCLK_MUX;

TIMEPARAGRANULARITY_X1

B - 2.3

(3)

B + 1.9 B - 2.3

(3)

B + 1.9

td(clkH-be[x]nIV) Delay time, output clock GPMC_CLK

rising edge to output lower byte

enable and command latch enable

GPMC_BE0n_CLE, output upper byte

enable GPMC_BE1n invalid

(11)

div_by_1_mode;

GPMC_FCLK_MUX;

TIMEPARAGRANULARITY_X1

D -

2.3(4)

D + 1.9 D - 2.3

(4)

D + 1.9

td(clkL-be[x]nIV)

Delay time, GPMC_CLK falling edge

to GPMC_BE0n_CLE, GPMC_BE1n

invalid

(12)

div_by_1_mode;

GPMC_FCLK_MUX;

TIMEPARAGRANULARITY_X1

D - 2.3

(4)

D + 1.9 D - 2.3

(4)

D + 1.9

td(clkL-be[x]nIV). Delay time, GPMC_CLK falling edge

to GPMC_BE0n_CLE, GPMC_BE1n

invalid

(13)

div_by_1_mode;

GPMC_FCLK_MUX;

TIMEPARAGRANULARITY_X1

D - 2.3

(4)

D + 1.9 D - 2.3

(4)

D + 1.9

td(clkH-advn)

Delay time, output clock GPMC_CLK

rising edge to output address

valid and address latch enable

GPMC_ADVn_ALE transition

div_by_1_mode;

GPMC_FCLK_MUX;

TIMEPARAGRANULARITY_X1;

no extra_delay

G -

2.3(7)

G + 4.5 G - 2.3

(7)

G + 4.5

td(clkH-advnIV)

Delay time, output clock GPMC_CLK

rising edge to output address

valid and address latch enable

GPMC_ADVn_ALE invalid

div_by_1_mode;

GPMC_FCLK_MUX;

TIMEPARAGRANULARITY_X1;

no extra_delay

D - 2.3

(4)

D + 4.5 D - 2.3

(4)

D + 4.5

F10 td(clkH-oen)

Delay time, output clock GPMC_CLK

rising edge to output enable

GPMC_OEn_REn transition

div_by_1_mode;

GPMC_FCLK_MUX;

TIMEPARAGRANULARITY_X1;

no extra_delay

H -

2.3(8)

H + 3.5 H - 2.3

(8)

H + 3.5

F11 td(clkH-oenIV)

Delay time, output clock GPMC_CLK

rising edge to output enable

GPMC_OEn_REn invalid

div_by_1_mode;

GPMC_FCLK_MUX;

TIMEPARAGRANULARITY_X1;

no extra_delay

H - 2.3

(8)

H + 3.5 H - 2.3

(8)

H + 3.5

F14 td(clkH-wen)

Delay time, output clock GPMC_CLK

rising edge to output write enable

GPMC_WEn transition

div_by_1_mode;

GPMC_FCLK_MUX;

TIMEPARAGRANULARITY_X1;

no extra_delay

I - 2.3

(9)

I + 4.5

I - 2.3

(9)

I + 4.5

F15 td(clkH-do)

Delay time, output clock GPMC_CLK

rising edge to output data

GPMC_AD[n:0](1) transition

(11)

div_by_1_mode;

GPMC_FCLK_MUX;

TIMEPARAGRANULARITY_X1

J - 2.3

(10)

J + 2.7

J - 2.3

(10)

J + 2.7

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AM6442, AM6441, AM6421, AM6412, AM6411

SPRSP56D – JANUARY 2021 – REVISED JULY 2022

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