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AM6421...ALV 数据表(PDF) 178 Page - Texas Instruments |
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AM6421...ALV 数据表(HTML) 178 Page - Texas Instruments |
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178 / 244 page  Table 7-76. MMC1 DLL Delay Mapping for all Timing Modes (continued) REGISTER NAME MMCSD1_SS_PHY_CTRL_4_REG MMCSD1_SS_PHY_CTRL_5_REG BIT FIELD [20] [15:12] [8] [4:0] [2:0] BIT FIELD NAME OTAPDLYENA OTAPDLYSEL ITAPDLYENA ITAPDLYSEL CLKBUFSEL MODE DESCRIPTION DELAY ENABLE DELAY VALUE INPUT DELAY ENABLE INPUT DELAY VALUE DELAY BUFFER DURATION UHS-I DR50 4-bit PHY operating 1.8 V, 50 MHz 0x1 0x9 0x1 Tuning(1) 0x7 UHS-I SDR104 4-bit PHY operating 1.8, V 200 MHz 0x1 0x6 0x1 Tuning(1) 0x7 (1) Tuning means this mode requires a tuning algorithm to be used for optimal input timing Table 7-77 presents timing conditions for MMC1. Table 7-77. MMC1 Timing Conditions PARAMETER MIN MAX UNIT Input Conditions SRI Input slew rate Default Speed, High Speed 0.69 2.06 V/ns UHS–I SDR12, UHS–I SDR25 0.34 1.34 V/ns UHS–I DDR50 1 2 V/ns Output Conditions CL Output load capacitance UHS–I DDR50 3 10 pF All other modes 1 10 pF PCB Connectivity Requirements td(Trace Delay) Propagation delay of each trace UHS–I DDR50 240 1134 ps All other modes 126 1386 ps td(Trace Mismatch Delay) Propagation delay mismatch across all traces UHS–I DDR50, UHS–I SDR104 20 ps All other modes 100 ps AM6442, AM6441, AM6421, AM6412, AM6411 SPRSP56D – JANUARY 2021 – REVISED JULY 2022 www.ti.com 178 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: AM6442 AM6441 AM6421 AM6412 AM6411 |
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