AM6421...ALV datasheet(193/244 Pages) TI

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(2)

M = OSPI_DEV_DELAY_REG[D_INIT_FLD]

(3)

N = OSPI_DEV_DELAY_REG[D_AFTER_FLD]

(4)

R = refclk cycle time in ns

OSPI_CLK

OSPI_TIMING_02

OSPI_CSn

O10

O11

O12

OSPI_D[i:0]

Figure 7-88. OSPI0 Switching Characteristics – Tap SDR, No Loopback

7.10.5.14.2.2 OSPI0 Tap DDR Timing

Table 7-105, Figure 7-89, Table 7-106, and Figure 7-90 present timing requirements and switching

characteristics for OSPI0 Tap DDR Mode.

Table 7-105. OSPI0 Timing Requirements – Tap DDR Mode

see Figure 7-89

NO.

MODE

MIN

MAX

UNIT

O13

tsu(D-CLK)

Setup time, OSPI0_D[7:0] valid before

active OSPI0_CLK edge

No Loopback

(12.04 -

(0.975T(1)R(2)))

O14

th(CLK-D)

Hold time, OSPI0_D[7:0] valid after active

OSPI0_CLK edge

No Loopback

(1.84 +

(0.975T(1)R(2)))

(1)

T = OSPI_RD_DATA_CAPTURE_REG[DELAY_FLD]

(2)

R = refclk cycle time in ns

OSPI_CLK

O14

O13

OSPI_TIMING_03

OSPI_D[i:0]

O14

O13

Figure 7-89. OSPI0 Timing Requirements – Tap DDR, No Loopback

Table 7-106. OSPI0 Switching Characteristics – Tap DDR Mode

see Figure 7-90

NO.

PARAMETER

MODE

MIN

MAX

UNIT

tc(CLK)

Cycle time, OSPI0_CLK

tw(CLKL)

Pulse duration, OSPI0_CLK low

((0.475P(1)) - 0.3)

tw(CLKH)

Pulse duration, OSPI0_CLK high

((0.475P(1)) - 0.3)

td(CLK-CSn)

Delay time, OSPI0_CSn[3:0] active edge

to OSPI0_CLK rising edge

((0.475P(1)) +

((0.975M(2)R(4)) - 1)

((0.525P(1)) +

( 1.025M(2)R(4)) +

td(CLK-CSn)

Delay time, OSPI0_CLK rising edge to

OSPI0_CSn[3:0] inactive edge

((0.475P(1)) +

(0.975N(3)R(4)) - 1)

((0.525P(1)) +

(1.025N(3)R(4)) + 1)

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AM6442, AM6441, AM6421, AM6412, AM6411

SPRSP56D – JANUARY 2021 – REVISED JULY 2022

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