SAF7741 datasheet(2/83 Pages) NXP

2 / 83 page

SAF7741_5

Objective data sheet

Rev. 05 — 09 May 2008

2 of 83

NXP Semiconductors

SAF7741HV

Dual IF car radio and audio DSP (N1F)

Features

2.1 Hardware features

SAF7741HV hardware is configured by firmware and host software to meet specific

customer requirements. The firmware is defined by the Read-Only Memory (ROM) code

associated with each DSP.

Remark: The list below describes the maximum hardware configuration. Customers

should consult with NXP to identify the best method of supporting their own particular

requirements.

Two IF data-paths of either 2

× IF 10.7 MHz or 2 × low IF 300 kHz input

Remark: The combination of 1 x IF and 1 x low IF is not supported.

Two 5th order Sigma-Delta (

ΣΔ) IF ADCs for FM/AM/WB (Weather-band) and digital

radio at either IF = 10.7 MHz or low IF = 300 kHz

IF signal quadrature-mixing and down-sampling with signal level generation

Automatic Gain Control (AGC) of the radio front-end chip in three steps (6 dB for each

step) for the TEF6730 tuner and seven steps (6 dB for each step) for the TEF7000

tuner

AGC control of the TEF6730 tuner front-end PIN diodes, with an analog signal via the

Radio General-Purpose DAC (RGP DAC) output: one DAC for each radio data path

Integrated IF filter with bandwidth of 100 kHz or 400 kHz

Two wideband outputs for external digital radio decoding; one output for each

data-path

Two Radio Data System (RDS) decoders

Five bit-stream, 3rd order audio,

ΣΔ ADCs with an anti-aliasing broadband input-filter

Eight configurable analog inputs (differential/stereo/mono) connected to any of the five

ADCs using an analog switchbox

Dedicated DSP for the Sample Rate Converter (SRC)

Audio Host Inter-IC Sound (IIS) Input/Output (I/O) port, with eight/ten outputs and eight

inputs with an option for slaving the DSP to an external master sample-rate

Audio Host IIS Bit-Clock (BCK) and Word-Size (WS) available simultaneously at

full-rate and half-rate

Four independent IIS inputs and two independent digital Sony/Philips Digital Interface

Format (SPDIF) inputs also configurable for Digital Versatile Disc/Digital Video Device

(DVD) multi-channel data inputs

Radio Host IIS master with separate data in and out lines

IIS output with buffer for eight samples for radio applications

WatchDog (WDOG) to monitor execution of the DSP main software loop

Phase-Lock Loop (PLL) to generate the DSP clock from the oscillator crystal

PLL to generate the audio reference sample-rate clock

Internal voltage regulator for the 1.8 V supply

I2C (Inter-IC Communication) bus-controlled

Possibility of powering down unused blocks to reduce power dissipation

Qualified in accordance with AEC-Q100

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