SAF7741 datasheet(55/83 Pages) NXP

55 / 83 page

SAF7741_5

Objective data sheet

Rev. 05 — 09 May 2008

55 of 83

NXP Semiconductors

SAF7741HV

Dual IF car radio and audio DSP (N1F)

To prevent the system from locking up when the WS_HOST or FS_SYS input drops out,

the audio PLL switches automatically to the crystal oscillator input for generating the

appropriate frequency. For example, if the WS_HOST input for Fs = 48 kHz drops out the

audio PLL selects the crystal oscillator as input and generates the 512

× Fs output

frequency with Fs = 48 kHz.

Table 22 lists all the targeted output frequencies. The first column in the table gives the

three possible inputs of the audio PLL while the second column lists the corresponding

input frequencies. The third column shows the targeted sampling frequencies that are

used to derive the output frequency of the PLL as shown in the last column of the table,

i.e. 512

× Fs.

Remark: When the audio PLL is set to lock onto either WS_HOST or FS_SYS the actual

frequency of the input signal is allowed to deviate by up to 20% from the target Fs.

However, optimum audio performance of the SAF7741HV is guaranteed only at 44.1 kHz

and 48 kHz.

7.8.6 Tuner clock generation circuit

To decrease total system cost, the crystal oscillator of SAF7741HV can also be used as

reference clock for the tuner so that the external components of the the tuner’s own

crystal oscillator can be omitted. The technical advantage here is that the tuner and

SAF7741HV clock frequencies are coupled, which prevents performance deterioration as

a result of mismatched frequency domains.

The tuner clock generation circuit uses a differential output current to provide a 100

kHz/400 kHz reference clock. The reference frequency is derived from the crystal

oscillator. To get rid of the disturbances introduced by the digital dividers, the clock for the

current drivers is synchronized by the clean crystal oscillator clock. The differential output

current ensures that the interface between the tuner and SAF7741HV will not interfere

with the application. The output current depends on the number of connected tuners and

needs to be controlled by I2C. See Figure 39 for the dual tuner application.

For the TEF6730 the reference clock frequency can be set to 100 kHz.

Table 22.

List of frequencies generated by audio PLL

Input signal

Input signal fre-

quency

Targeted Fs (kHz)

Targeted output

frequency = 512

× Fs

Osc: Oscillator (41.6 Mhz) 41.6 MHz

44.1

22.583 MHz

41.6 MHz

24.576 MHz

41.6 MHz

49.152 MHz

WS_HOST

44.1 kHz

44.1

22.579 MHz

48 kHz

24.576 MHz

96 kHz

49.152 MHz

FS_SYS

256

× Fs

44.1

22.579 MHz

384

× Fs

44.1

22.579 MHz

512

× Fs

44.1

22.579 MHz

256

× Fs

24.576 MHz

384

× Fs

24.576 MHz

512

× Fs

24.576 MHz

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