DVR21 datasheet(195/416 Pages) MICROCHIP

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DS30010118D-page 195

PIC24FJ256GA705 FAMILY

CCPxCON2H: CCPx CONTROL 2 HIGH REGISTERS

R/W-0

U-0

R/W-0

R/W-1

OENSYNC

—OCFEN(1,2)

OCEEN(1,2)

OCDEN(1,2)

OCCEN(1,2)

OCBEN(1,2)

OCAEN(2)

bit 15

bit 8

R/W-0

U-0

R/W-0

ICGSM1

ICGSM0

—

AUXOUT1

AUXOUT0

ICS2

ICS1

ICS0

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

-n = Value at POR

‘1’ = Bit is set

‘0’ = Bit is cleared

x = Bit is unknown

bit 15

OENSYNC: Output Enable Synchronization bit

1 = Update by output enable bits occurs on the next Time Base Reset or rollover

0 = Update by output enable bits occurs immediately

bit 14

Unimplemented: Read as ‘0’

bit 13-8

OCxEN: Output Enable/Steering Control bits(1,2)

1 = OCMx pin is controlled by the CCPx module and produces an output compare or PWM signal

0 = OCMx pin is not controlled by the CCPx module; the pin is available to the port logic or another

peripheral multiplexed on the pin

bit 7-6

ICGSM<1:0>: Input Capture Gating Source Mode Control bits

11 = Reserved

10 = One-Shot mode: Falling edge from gating source disables future capture events (ICDIS = 1)

01 = One-Shot mode: Rising edge from gating source enables future capture events (ICDIS = 0)

00 = Level-Sensitive mode: A high level from gating source will enable future capture events; a low

level will disable future capture events

bit 5

Unimplemented: Read as ‘0’

bit 4-3

AUXOUT<1:0>: Auxiliary Output Signal on Event Selection bits

11 = Input capture or output compare event; no signal in Timer mode

10 = Signal output is defined by module operating mode (see Table 16-4)

01 = Time base rollover event (all modes)

00 =Disabled

bit 2-0

ICS<2:0>: Input Capture Source Select bits

111 = Reserved

110 = Reserved

101 = CLC2 output

100 = CLC1 output

011 = Comparator 3 output

010 = Comparator 2 output

001 = Comparator 1 output

000 = Input Capture x (ICMx) I/O pin

Note 1:

OCFEN through OCBEN (bits<13:9>) are not implemented in all CCPx modules.

OCFEN through OCAEN (bits<13:8>) are not dedicated pins in all CCPx modules, PPS has to be used.

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