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DVR21 数据表(PDF) 197 Page - Microchip Technology |
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DVR21 数据表(HTML) 197 Page - Microchip Technology |
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197 / 416 page  2016-2018 Microchip Technology Inc. DS30010118D-page 197 PIC24FJ256GA705 FAMILY REGISTER 16-6: CCPxCON3H: CCPx CONTROL 3 HIGH REGISTERS R/W-0 R/W-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0 R/W-0 OETRIG OSCNT2 OSCNT1 OSCNT0 —OUTM2(1) OUTM1(1) OUTM0(1) bit 15 bit 8 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — —POLACE POLBDF(1) PSSACE1 PSSACE0 PSSBDF1(1) PSSBDF0(1) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 OETRIG: CCPx Dead-Time Select bit 1 = For Triggered mode (TRIGEN = 1): Module does not drive enabled output pins until triggered 0 = Normal output pin operation bit 14-12 OSCNT<2:0>: One-Shot Event Count bits 111 = Extends one-shot event by seven time base periods (eight time base periods total) 110 = Extends one-shot event by six time base periods (seven time base periods total) 101 = Extends one-shot event by five time base periods (six time base periods total) 100 = Extends one-shot event by four time base periods (five time base periods total) 011 = Extends one-shot event by three time base periods (four time base periods total) 010 = Extends one-shot event by two time base periods (three time base periods total) 001 = Extends one-shot event by one time base period (two time base periods total) 000 = Does not extend one-shot trigger event bit 11 Unimplemented: Read as ‘0’ bit 10-8 OUTM<2:0>: PWMx Output Mode Control bits(1) 111 = Reserved 110 = Output Scan mode 101 = Brush DC Output mode, forward 100 = Brush DC Output mode, reverse 011 = Reserved 010 = Half-Bridge Output mode 001 = Push-Pull Output mode 000 = Steerable Single Output mode bit 7-6 Unimplemented: Read as ‘0’ bit 5 POLACE: CCPx Output Pins, OCMxA, OCMxC and OCMxE, Polarity Control bit 1 = Output pin polarity is active-low 0 = Output pin polarity is active-high bit 4 POLBDF: CCPx Output Pins, OCMxB, OCMxD and OCMxF, Polarity Control bit (1) 1 = Output pin polarity is active-low 0 = Output pin polarity is active-high bit 3-2 PSSACE<1:0>: PWMx Output Pins, OCMxA, OCMxC and OCMxE, Shutdown State Control bits 11 = Pins are driven active when a shutdown event occurs 10 = Pins are driven inactive when a shutdown event occurs 0x = Pins are tri-stated when a shutdown event occurs bit 1-0 PSSBDF<1:0>: PWMx Output Pins, OCMxB, OCMxD, and OCMxF, Shutdown State Control bits (1) 11 = Pins are driven active when a shutdown event occurs 10 = Pins are driven inactive when a shutdown event occurs 0x = Pins are in a high-impedance state when a shutdown event occurs Note 1: These bits are implemented in the MCCP1 module only. |
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