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DVR21 数据表(PDF) 234 Page - Microchip Technology |
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DVR21 数据表(HTML) 234 Page - Microchip Technology |
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234 / 416 page  PIC24FJ256GA705 FAMILY DS30010118D-page 234 2016-2018 Microchip Technology Inc. bit 3 BRGH: High Baud Rate Enable bit 1 = High-Speed mode (4 BRG clock cycles per bit) 0 = Standard Speed mode (16 BRG clock cycles per bit) bit 2-1 PDSEL<1:0>: Parity and Data Selection bits 11 = 9-bit data, no parity 10 = 8-bit data, odd parity 01 = 8-bit data, even parity 00 = 8-bit data, no parity bit 0 STSEL: Stop Bit Selection bit 1 = Two Stop bits 0 = One Stop bit REGISTER 19-1: UxMODE: UARTx MODE REGISTER (CONTINUED) Note 1: If UARTEN = 1, the peripheral inputs and outputs must be configured to an available RPn/RPIn pin. For more information, see Section 11.5 “Peripheral Pin Select (PPS)”. 2: This feature is only available for the 16x BRG mode (BRGH = 0). |
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