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DVR21 数据表(PDF) 235 Page - Microchip Technology |
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DVR21 数据表(HTML) 235 Page - Microchip Technology |
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235 / 416 page  2016-2018 Microchip Technology Inc. DS30010118D-page 235 PIC24FJ256GA705 FAMILY REGISTER 19-2: UxSTA: UARTx STATUS AND CONTROL REGISTER R/W-0 R/W-0 R/W-0 R/W-0 HC/R/W-0 R/W-0 HSC/R-0 HSC/R-1 UTXISEL1 UTXINV(1) UTXISEL0 URXEN UTXBRK UTXEN(2) UTXBF TRMT bit 15 bit 8 R/W-0 R/W-0 R/W-0 HSC/R-1 HSC/R-0 HSC/R-0 HS/R/C-0 HSC/R-0 URXISEL1 URXISEL0 ADDEN RIDLE PERR FERR OERR URXDA bit 7 bit 0 Legend: C = Clearable bit HSC = Hardware Settable/Clearable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown HS = Hardware Settable bit HC = Hardware Clearable bit bit 15,13 UTXISEL<1:0>: UARTx Transmission Interrupt Mode Selection bits 11 = Reserved; do not use 10 = Interrupt when a character is transferred to the Transmit Shift Register (TSR), and as a result, the transmit buffer becomes empty 01 = Interrupt when the last character is shifted out of the Transmit Shift Register; all transmit operations are completed 00 = Interrupt when a character is transferred to the Transmit Shift Register (this implies there is at least one character open in the transmit buffer) bit 14 UTXINV: UARTx IrDA® Encoder Transmit Polarity Inversion bit(1) IREN = 0: 1 = UxTX Idle state is ‘0’ 0 = UxTX Idle state is ‘1’ IREN = 1: 1 = UxTX Idle state is ‘1’ 0 = UxTX Idle state is ‘0’ bit 12 URXEN: UARTx Receive Enable bit 1 = Receive is enabled, UxRX pin is controlled by UARTx 0 = Receive is disabled, UxRX pin is controlled by the port bit 11 UTXBRK: UARTx Transmit Break bit 1 = Sends Sync Break on next transmission – Start bit, followed by twelve ‘0’ bits, followed by Stop bit; cleared by hardware upon completion 0 = Sync Break transmission is disabled or completed bit 10 UTXEN: UARTx Transmit Enable bit(2) 1 = Transmit is enabled, UxTX pin is controlled by UARTx 0 = Transmit is disabled, any pending transmission is aborted and the buffer is reset; UxTX pin is controlled by the port bit 9 UTXBF: UARTx Transmit Buffer Full Status bit (read-only) 1 = Transmit buffer is full 0 = Transmit buffer is not full, at least one more character can be written bit 8 TRMT: Transmit Shift Register Empty bit (read-only) 1 = Transmit Shift Register is empty and transmit buffer is empty (the last transmission has completed) 0 = Transmit Shift Register is not empty, a transmission is in progress or queued Note 1: The value of this bit only affects the transmit properties of the module when the IrDA® encoder is enabled (IREN = 1). 2: If UARTEN = 1, the peripheral inputs and outputs must be configured to an available RPn/RPIn pin. For more information, see Section 11.5 “Peripheral Pin Select (PPS)”. |
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