DVR21 datasheet(291/416 Pages) MICROCHIP

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DS30010118D-page 291

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24.4

Achieving Maximum A/D

Converter Performance

In order to get the shortest overall conversion time

(called the ‘throughput’) while maintaining accuracy,

several factors must be considered. These are

described in detail below.

• Dependence of AVDD – If the AVDD supply is < 2.7V,

the Charge Pump Enable bit (PUMPEN,

AD1CON3<13>) should be set to ‘1’. The input

channel multiplexer has a varying resistance with

AVDD (the lower AVDD, the higher the internal

switch resistance). The charge pump provides a

higher internal AVDD to keep the switch resistance

as low as possible.

• Dependence on TAD – The ADC timing is driven

by TAD, not TCYC. Selecting the TAD time correctly

is critical to getting the best ADC throughput. It is

important to note that the overall ADC throughput

is not simply the ‘Conversion Time’ of the SAR. It

is the combination of the Conversion Time, the

Sample Time and additional TAD delays for

internal synchronization logic.

• Relationship between TCYC and TAD – There is

not a fixed 1:1 timing relationship between TCYC

and TAD. The fastest possible throughput is funda-

mentally set by TAD (min), not by TCYC. The TAD

time is set as a programmable integer multiple of

TCYC by the ADCS<7:0> bits. Referring to

Table 32-25, the TAD (min) time is greater than the

4 MHz period of the dedicated ADC RC clock

generator. Therefore, TAD must be two TCYC in

order to use the RC clock for fastest throughput.

The TAD (min) is a multiple of 3.597 MHz as

opposed to 4 MHz. To run as fast as possible,

TCYC must be a multiple of TAD (min) because

values of ADCSx are integers. For example, if a

standard ‘color burst’ crystal of 14.31818 MHz is

used, TCYC is 279.4 ns, which is very close to TAD

(min) and the ADC throughput is optimal. Running

at 16 MHz will actually reduce the throughput,

because TAD will have to be 500 ns as the TCYC of

250 ns violates TAD (min).

• Dependence on driving Source Resistance (RS) –

Certain transducers have high output impedance

(> 2.5 k

). Having a high RS will require

longer sampling time to charge the S/H cap

through the resistance path (see Figure 25-3).

The worst case is a full-range voltage step of

AVSS to AVDD with the sampling cap at AVSS. The

capacitor time constant is (RS + RIC + RSS)

(CHOLD) and the sample time needs to be six time

constants minimum (eight are preferred). Since

the ADC logic timing is TAD-based, the sample

time (in TAD) must be long enough, over all condi-

tions, to charge/discharge CHOLD. Do not assume

one TAD is sufficient sample time; longer times

may be required to achieve the accuracy needed

by the application. The value of CHOLD is 40 pF.

A small amount of charge is present at the ADC

input pin when the sample switch is closed. If RS is

high, this will generate a DC error exceeding

one LSB. Keeping RS < 50

 is recommenced for

best results. The error can also be reduced by

increasing sample time (a 2 k

 value of RS

requires a 3 µS sample time to eliminate the error).

• Calculating Throughput – The throughput of the

ADC is based on TAD. The throughput is given by:

where:

Sample Time is the calculated TAD periods for the

application. SAR Conversion Time is 12 TAD for

10-bit and 14 TAD for 12-bit conversions. Clock

Sync Time is 2.5 TAD (worst case).

Example: For a 12-bit ADC throughput, if using

FRC = 8 MHz and the Sample Time is one TAD, the

use of an 8 MHz FRC means the TCYC = 250 ns and

this requires: TAD = 2 TCYC = 500 ns. Therefore, the

throughput is:

Note that the clock sync delay could be as little as

1.5 TAD, which could produce 121 KS/sec, but that

cannot be ensured as the timing relationship is asyn-

chronous and not specified. The worst case timing of

2.5 TAD should be used to calculate throughput.

Example: A certain transducer has a 20 k

 output

impedance. If AVDD is 3.0, the maximum sample

time needed would be determined by the following:

If TAD = 500 ns, this requires a Sample Time of 4.95 µs/

500 ns = 10 TAD (for a full-step voltage on the

transducer output). RSS is 350

 because AVDD is

above 2.7V.

Throughput = 1/(Sample Time + SAR Conversion Time +

Clock Sync Time)

Throughput = 1/(500 ns) + (14 * 500 ns) + (2.5 * 500 ns) =

114.28KS/sec

Sample Time = 6 * (RS +RIC + RSS) * CHOLD

= 6 * (20K + 250 + 350) * 40 pF

= 4.95 µS

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