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DVR21 数据表(PDF) 295 Page - Microchip Technology |
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DVR21 数据表(HTML) 295 Page - Microchip Technology |
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295 / 416 page  2016-2018 Microchip Technology Inc. DS30010118D-page 295 PIC24FJ256GA705 FAMILY REGISTER 24-2: AD1CON2: A/D CONTROL REGISTER 2 R/W-0 R/W-0 R/W-0 r-0 R/W-0 R/W-0 U-0 U-0 PVCFG1 PVCFG0 NVCFG0 — BUFREGEN CSCNA — — bit 15 bit 8 R-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 BUFS SMPI4 SMPI3 SMPI2 SMPI1 SMPI0 BUFM ALTS bit 7 bit 0 Legend: r = Reserved bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-14 PVCFG<1:0>: A/D Converter Positive Voltage Reference Configuration bits 1x = Unimplemented, do not use 01 =External VREF+ 00 =AVDD bit 13 NVCFG0: A/D Converter Negative Voltage Reference Configuration bit 1 = External VREF- 0 = AVSS bit 12 Reserved: Maintain as ‘0’ bit 11 BUFREGEN: A/D Buffer Register Enable bit 1 = Conversion result is loaded into the buffer location determined by the converted channel 0 = A/D result buffer is treated as a FIFO bit 10 CSCNA: Scan Input Selections for CH0+ During Sample A bit 1 = Scans inputs 0 = Does not scan inputs bit 9-8 Unimplemented: Read as ‘0’ bit 7 BUFS: Buffer Fill Status bit When DMAEN = 1 and DMABM = 1: 1 = A/D is currently filling the destination buffer from [buffer start + (buffer size/2)] to [buffer start + (buffer size – 1)]. User should access data located from [buffer start] to [buffer start + (buffer size/2) – 1]. 0 = A/D is currently filling the destination buffer from [buffer start] to [buffer start + (buffer size/2) – 1]. User should access data located from [buffer start + (buffer size/2)] to [buffer start + (buffer size – 1)]. When DMAEN = 0: 1 = A/D is currently filling ADC1BUF13-ADC1BUF25, user should access data in ADC1BUF0-ADC1BUF12 0 = A/D is currently filling ADC1BUF0-ADC1BUF12, user should access data in ADC1BUF13-ADC1BUF25 |
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