D301 datasheet(64/416 Pages) MICROCHIP

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PIC24FJ256GA705 FAMILY

DS30010118D-page 64

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5.1

Summary of DMA Operations

The DMA Controller is capable of moving data between

addresses according to a number of different parameters.

Each of these parameters can be independently

configured for any transaction; in addition, any or all of

the DMA channels can independently perform a differ-

ent transaction at the same time. Transactions are

classified by these parameters:

• Source and destination (SFRs and data RAM)

• Data size (byte or word)

• Trigger source

• Transfer mode (One-Shot, Repeated or

Continuous)

• Addressing modes (Fixed Address or Address

Blocks, with or without Address Increment/

Decrement)

In addition, the DMA Controller provides channel priority

arbitration for all channels.

5.1.1

SOURCE AND DESTINATION

Using the DMA Controller, data may be moved between

any two addresses in the Data Space. The SFR space

(0000h to 07FFh), or the data RAM space (0800h to

FFFFh), can serve as either the source or the destina-

tion. Data can be moved between these areas in either

direction or between addresses in either area. The four

different combinations are shown in Figure 5-2.

If it is necessary to protect areas of data RAM, the DMA

Controller allows the user to set upper and lower address

boundaries for operations in the Data Space above the

SFR space. The boundaries are set by the DMAH and

DMAL Limit registers. If a DMA channel attempts an

operation outside of the address boundaries, the

transaction is terminated and an interrupt is generated.

5.1.2

DATA SIZE

The DMA Controller can handle both 8-bit and 16-bit

transactions. Size is user-selectable using the SIZE bit

(DMACHn<1>). By default, each channel is configured

for word-sized transactions. When byte-sized transac-

tions are chosen, the LSb of the source and/or

destination address determines if the data represents

the upper or lower byte of the data RAM location.

5.1.3

TRIGGER SOURCE

The DMA Controller can use any one of the device’s

interrupt sources to initiate a transaction. The DMA

Trigger sources are listed in reverse order of their

natural interrupt priority and are shown in Table 5-1.

Since the source and destination addresses for any

transaction can be programmed independently of the

trigger source, the DMA Controller can use any trigger

to perform an operation on any peripheral. This also

allows DMA channels to be cascaded to perform more

complex transfer operations.

5.1.4

TRANSFER MODE

The DMA Controller supports four types of data

transfers, based on the volume of data to be moved for

each trigger.

• One-Shot: A single transaction occurs for each

trigger.

• Continuous: A series of back-to-back transactions

occur for each trigger; the number of transactions

is determined by the DMACNTn transaction

counter.

• Repeated One-Shot: A single transaction is

performed repeatedly, once per trigger, until the

DMA channel is disabled.

• Repeated Continuous: A series of transactions

are performed repeatedly, one cycle per trigger,

until the DMA channel is disabled.

All transfer modes allow the option to have the source

and destination addresses, and counter value automat-

ically reloaded after the completion of a transaction.

Repeated mode transfers do this automatically.

5.1.5

ADDRESSING MODES

The DMA Controller also supports transfers between

single addresses or address ranges. The four basic

options are:

• Fixed-to-Fixed: Between two constant addresses

• Fixed-to-Block: From a constant source address

to a range of destination addresses

• Block-to-Fixed: From a range of source addresses

to a single, constant destination address

• Block-to-Block: From a range to source

addresses to a range of destination addresses

The option to select auto-increment or auto-decrement

of source and/or destination addresses is available for

Block Addressing modes.

In addition to the four basic modes, the DMA Controller

also supports Peripheral Indirect Addressing (PIA)

mode, where the source or destination address is gen-

erated jointly by the DMA Controller and a PIA capable

peripheral. When enabled, the DMA channel provides

a base source and/or destination address, while the

peripheral provides a fixed range offset address.

For PIC24FJ256GA705 family devices, the 12-bit A/D

Converter module is the only PIA capable peripheral.

Details for its use in PIA mode are provided in

Section 24.0 “12-Bit A/D Converter with Threshold

Detect”.

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