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D301 数据表(PDF) 97 Page - Microchip Technology

部件名 D301
功能描述  16-Bit General Purpose Microcontrollers with 256-Kbyte Flash and 16-Kbyte RAM in Low Pin Count Packages
PDF  416 Pages
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制造商  MICROCHIP [Microchip Technology]
网页  http://www.microchip.com
标志 MICROCHIP - Microchip Technology

D301 数据表(HTML) 97 Page - Microchip Technology

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 2016-2018 Microchip Technology Inc.
DS30010118D-page 97
PIC24FJ256GA705 FAMILY
9.0
OSCILLATOR CONFIGURATION
The oscillator system for the PIC24FJ256GA705 family
devices has the following features:
• An On-Chip PLL Block to provide a Range of
Frequency Options for the System Clock
• Software-Controllable Switching between Various
Clock Sources
• Software-Controllable Postscaler for Selective
Clocking of CPU for System Power Savings
• A Fail-Safe Clock Monitor (FSCM) that Detects
Clock Failure and Permits Safe Application
Recovery or Shutdown
• A Separate and Independently Configurable System
Clock Output for Synchronizing External Hardware
A simplified diagram of the oscillator system is shown
in Figure 9-1.
FIGURE 9-1:
PIC24FJ256GA705 FAMILY CLOCK DIAGRAM
Note:
This data sheet summarizes the features
of this group of PIC24F devices. It is not
intended to be a comprehensive refer-
ence source. For more information, refer
to the “dsPIC33/PIC24 Family Reference
Manual”, “Oscillator” (DS39700), which
is available from the Microchip website
(www.microchip.com). The information
in this data sheet supersedes the
information in the FRM.
PIC24FJ256GA705 Family
Secondary Oscillator
SOSCEN
Enable
Oscillator
SOSCO
SOSCI
WDT, Other Modules
OSCI
OSCO
Primary Oscillator
XT, HS, EC
CPU
Peripherals
RCDIV<2:0>
Timer, CCP, RTCC, CLC, WDT, PWRT
OSCFDIV
SOSC
Clock Control Logic
FSCM
DOZE<14:12>
CLKO
XTPLL, HSPLL
ECPLL,FRCPLL
PLL &
DIV
PLLMODE<3:0> CPDIV<1:0>
PLL
CCP
LPRC
FRC
DIV<14:0>
LPRC
Oscillator
FRC
Divider
÷ n
WDT, RTCC, CLC



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