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STM32L4 数据表(PDF) 7 Page - STMicroelectronics |
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STM32L4 数据表(HTML) 7 Page - STMicroelectronics |
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7 / 33 page ![]() STM32L4+ System Architecture 6 32-bit multilayer AHB bus matrix, 9 Masters, 11 Slaves DMA1 DMA2 DMA2D LCD-TFT Cortex-M4 SDMMC1 GFXMMU(1) SDMMC2(2) SRAM1 SRAM2 GFXMMU(1) AHB1 Peripheral FMC OCTOPI1 FLASH up to 2 MB BusMatrix-S SRAM3 ICode DCode AHB2 Peripheral OCTOPI2 (1) GFXMMU is only available on STM32L4P5xx/4Q5xx devices (2) SDMMC2 is only available on STM32L4Rxxx/4Sxxx devices The STM32L4+ main system architecture consists of 32-bit multilayer AHB bus matrix that interconnects 9 masters and 11 slaves. The main differences with STM32L476/486 devices are highlighted in pink square. |
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